🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
-
Updated
Apr 30, 2026 - Python
#
vyges
Here are 32 public repositories matching this topic...
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.
asic fpga pipeline signal-processing rad verilog digital-signal-processing apb ip-core hardware-ip vyges vyges-ip ix-2
-
Updated
Jul 15, 2026 - SystemVerilog
A fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature signal processing. Optimized for FPGA and ASIC implementations with configurable precision and maximum throughput.
-
Updated
Oct 8, 2025 - SystemVerilog
VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.
eda verilog systemverilog semiconductor cocotb browser-ide github-codespaces chip-design open-source-silicon vyges vyges-ip vybox vybox-lite
-
Updated
Feb 20, 2026 - JavaScript
Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.
rust digital eda semiconductor silicon static-timing-analysis signal-integrity eda-tools vyges sign-off open-silicon vyges-loom
-
Updated
Jul 19, 2026 - Rust
Layout-vs-schematic: SPICE netlist comparison with clear divergence diagnostics.
rust digital analog eda semiconductor mixed-signal silicon lvs eda-tools vyges open-silicon vyges-loom layout-vs-schematic
-
Updated
Jul 19, 2026 - Rust
A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.
-
Updated
Oct 8, 2025 - SystemVerilog
A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz
-
Updated
Oct 8, 2025 - Python
Clean-room container for building RTL → GDSII: a slim, pinned open-source EDA toolchain (Yosys · Verilator · OpenROAD · Magic · KLayout · Netgen · ngspice + sky130/gf180 PDKs), built from scratch on GitHub Actions and published to GHCR.
docker magic asic container eda vlsi yosys semiconductor klayout netgen ngspice gdsii physical-design openroad sky130 chip-design gf180mcu open-source-silicon rtl-to-gdsii vyges
-
Updated
Jul 18, 2026 - Dockerfile
📋 Vyges Metadata Specification - Standardized format for hardware IP discovery and integration
-
Updated
Jun 9, 2026 - HTML
Public release home for the Vyges CLI — prebuilt binaries + curl/PowerShell installers (catalog, PDK, and Loom-engine installs). Homebrew tap: vyges/homebrew-tap.
-
Updated
Jul 24, 2026
Vyges open-PDK catalog: index.json + full PDK descriptors
-
Updated
Jul 19, 2026 - Python
Liberty characterization — SPICE + PDK models to .lib (NLDM + CCS), parallel-SPICE orchestration.
rust digital eda spice characterization liberty semiconductor silicon eda-tools vyges open-silicon vyges-loom
-
Updated
Jul 19, 2026 - Rust
STA-driven buffer insertion: split high-fanout / over-transition nets to fix slew and timing.
rust digital optimization eda semiconductor silicon eda-tools vyges open-silicon vyges-loom buffer-insertion
-
Updated
Jul 19, 2026 - Rust
Post-route hold-fix ECO: insert series delay cells on hold-violating capture pins to close hold timing.
rust digital optimization eda semiconductor silicon sta timing-closure eda-tools vyges open-silicon vyges-loom hold-fix
-
Updated
Jul 19, 2026 - Rust
STA-driven Vt swapping: trade threshold-voltage flavors (iso-footprint) to cut leakage while holding timing, or to close setup.
-
Updated
Jul 19, 2026 - Rust
Combinational logic equivalence check: two gate-level netlists in, an equivalence verdict (with counter-example) out.
rust digital bdd eda formal-verification semiconductor eda-tools equivalence-checking vyges open-silicon vyges-loom
-
Updated
Jul 19, 2026 - Rust
Power analysis: per-instance leakage + dynamic power and the activity map that closes char -> power -> em-ir.
-
Updated
Jul 19, 2026 - Rust
Improve this page
Add a description, image, and links to the vyges topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the vyges topic, visit your repo's landing page and select "manage topics."