5 Day TCL begginer to advanced training workshop by VSD

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

A web-based tool for parsing and visualizing FPGA. It provides an interactive graph representation of signal propagation, helping engineers and students analyze delays, interconnections, and logic components inside an FPGA.

A collection of Schematics, PCBs and VLSI work on various platforms

Personal GitHub repository for experiments, project tests, and general development work.

The RISCV project was converted from RTL code to GDS II format using 14nm PDKs. This was implemented with the ICC2 and Design Compiler NXT EDA tools from Synopsys, following a Flat Design Style

Design and simulation of 16-bit Ripple Carry and Weinberger Adders using Cadence Virtuoso. Includes full adder modeling, schematic creation, waveform analysis, and detailed delay-power comparison.

A practical day-by-day journey exploring Digital IC Design using Cadence Virtuoso — from schematics to layouts, DRC/LVS checks, parasitic extraction, and timing analysis.

Use GPT-4 to generate, simulate, and visualize Verilog modules from natural language prompts.

物性・回路・プロセス・設計・テストを貫く一貫教育体系。 基礎から応用・実践までの構造的理解を重視。An integrated educational framework covering semiconductor physics, circuit design, fabrication processes, and testing. Emphasizes structured understanding from fundamentals to advanced and practical applications.