Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

The next generation of OpenLane, rewritten from scratch with a modular architecture

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Index of the fully open source process design kits (PDKs) maintained by Google.

Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.

Raw data collected about the SKY130 process technology.

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

A simple MOSFET model with only 5-DC-parameters for circuit simulation

Flip flop setup, hold & metastability explorer tool

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.

KLayout technology files for Skywater SKY130

Fully-differential asynchronous non-binary 12-bit SAR-ADC

Primitives for SKY130 provided by SkyWater.

open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists

Reinforcement learning assisted analog layout design flow.

SRAM build space for SKY130 provided by SkyWater.

This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130