ASIC implementation flow infrastructure, successor to OpenLane
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Jul 24, 2026 - Python
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openlane
Here are 118 public repositories matching this topic...
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
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Mar 26, 2022 - Verilog
Open source compliance automation for SOC 2, GDPR, ISO27001, NIST 800-53, and more
go graphql golang open-source security security-audit cybersecurity grc hacktoberfest iso27001 nist800-53 soc2 open-source-compliance compliance-as-code compliance-automation openlane cybersecurity-tools grc-automation
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Jul 23, 2026 - Go
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
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Sep 17, 2022
Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
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Nov 19, 2025 - Python
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
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Jan 23, 2024 - Verilog
the openlane ui - holds the openlane console and storybook
react typescript frontend nextjs compliance grc hacktoberfest iso27001 nist800-53 soc2 tailwindcss compliance-automation openlane hacktoberfest2025 tailwindcss-v4
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Jul 24, 2026 - TypeScript
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
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Jul 7, 2021
Gate-level visualization generator for SKY130-based chip designs.
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Jul 22, 2021 - Python
Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah
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Oct 19, 2024
Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.
opensource magic asic rtl icarus-verilog gtkwave yosys risc-v klayout ngspice vlsi-design asic-design openlane gdsii-flow system-on-chip-design
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Nov 25, 2025 - Verilog
🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
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Apr 30, 2026 - Python
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