#

vlsi-physical-design

Here are 69 public repositories matching this topic...

limbo018 / DREAMPlace

Deep learning toolkit-enabled VLSI placement

deep-learning pytorch gpu-acceleration vlsi vlsi-physical-design vlsi-placement

Updated Apr 15, 2025
C++

OpenTimer / OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design vlsi-physical-design sta electronic-design-automation vlsi-circuits static-timing-analysis

Updated May 26, 2023
Verilog

AUCOHL / DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

Updated Jun 15, 2024
Verilog

cuhk-eda / dr-cu

Dr. CU, VLSI Detailed Routing Tool Developed by CUHK

routing eda vlsi-physical-design

Updated Mar 20, 2023
C++

OpenTimer / Parser-Verilog

A Standalone Structural Verilog Parser

flex eda verilog cpp17 circuit computer-aided-design vlsi-physical-design electronic-design-automation vlsi-circuits bison-yacc

Updated Mar 31, 2022
Verilog

luckyrantanplan / nthu-route

VLSI EDA Global Router

router eda vlsi vlsi-physical-design electronic-design-automation vlsi-circuits globalrouter ispd lattice-graph multi-maze-routing

Updated Jan 22, 2018
C++

coriolis

lip6 / coriolis

Coriolis VLSI EDA Tool (LIP6)

eda vlsi-physical-design

Updated May 25, 2025
C++

AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

asic vlsi vlsi-physical-design rtl2gds openlane sky130 openlane-flow

Updated Sep 17, 2022

OpenTimer / Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

eda circuits cpp17 vlsi computer-aided-design vlsi-physical-design sta spef electronic-design-automation vlsi-circuits parasitic static-timing-analysis

Updated Aug 7, 2022
C++

chengengjie / salt

Steiner Shallow-Light Tree for VLSI Routing

graph-algorithms routing eda vlsi-physical-design

Updated Jul 11, 2024
C++

ieee-ceda-datc / RDF-2019

DATC RDF

routing eda cad vlsi logic-synthesis placement vlsi-physical-design design-automation design-flow vlsi-cad ieee-ceda ieee-ceda-datc vlsi-design-flow clock-tree

Updated Jul 31, 2020
Verilog

shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisa…

risc-v vlsi-physical-design electronics-engineering

Updated Jul 9, 2021
Verilog

VLSI-Physical-Design-Automation

twweeb / VLSI-Physical-Design-Automation

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

eda vlsi nthu vlsi-physical-design vlsi-design vlsi-placement vlsi-cad physical-design-automation vlsi-floorplan vlsi-routing two-way-min-cut fixed-outline global-placement global-routing

Updated Jan 23, 2021
C++

ShonTaware / OpenSource_Physical_Design

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

open-source vlsi-physical-design sky130 openlane-flow

Updated Feb 22, 2022

andrsmllr / magic_vlsi_examples

Some simple examples for the Magic VLSI physical chip layout tool.

asic vlsi vlsi-physical-design

Updated Mar 9, 2021

jinwookjungs / lefdef_util

A LEF/DEF Utility.

bookshelf vlsi placement vlsi-physical-design def vlsi-placement lef def-parser lef-parser datc-rdf

Updated Aug 15, 2019
Prolog

hibagus / 64pointFFTProcessor

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

signal-processing fast-fourier-transform digital-signal-processing vlsi-physical-design fpga-accelerator vlsi-design vlsi-project

Updated May 20, 2020
Verilog

UdayaShankarS / TCL-Scripting

Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference

vlsi-physical-design tcl-scripts vlsi-cad

Updated Dec 30, 2022
Tcl

fayizferosh / yosys-tcl-ui-report

5 Day TCL begginer to advanced training workshop by VSD

linux bash open-source csv workshop tcl synthesis yosys shell-scripting vlsi-physical-design hardware-description-language static-timing-analysis tcl-programming tcl-extensions tcl-procedures opentimer eda-tools

Updated Oct 18, 2023
Verilog

meeeeet / RTL-to-GDS-Implementation-of-SerDes

verilog vlsi-physical-design openroad asic-design rtl2gds

Updated Feb 22, 2024
Verilog

Improve this page

Add a description, image, and links to the vlsi-physical-design topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the vlsi-physical-design topic, visit your repo's landing page and select "manage topics."