A complete open-source design-for-testing (DFT) Solution
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Aug 30, 2025 - Swift
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vlsi-cad
Here are 30 public repositories matching this topic...
ACT hardware description language and core tools.
language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes
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Oct 14, 2025 - C++
DATC RDF
routing eda cad vlsi logic-synthesis placement vlsi-physical-design design-automation design-flow vlsi-cad ieee-ceda ieee-ceda-datc vlsi-design-flow clock-tree
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Jul 31, 2020 - Verilog
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
eda vlsi nthu vlsi-physical-design vlsi-design vlsi-placement vlsi-cad physical-design-automation vlsi-floorplan vlsi-routing two-way-min-cut fixed-outline global-placement global-routing
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Jan 23, 2021 - C++
Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference
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Dec 30, 2022 - Tcl
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
characterization power-analysis hspice spice-simulator vlsi-circuits timing-analysis vlsi-design vlsi-cad
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Feb 13, 2020 - C++
grayscale conversion system and simple convolution system
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Aug 25, 2021 - Verilog
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
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Dec 13, 2020 - Python
Course Project - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay
python algorithms networkx graph-theory clustering-algorithm kernighan-lin vlsi-cad circuit-partitioning eig-partitioning
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Dec 9, 2022 - Jupyter Notebook
Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.
processor-architecture ram hardware processor bus bluespec hardware-designs vlsi hardware-acceleration vlsi-physical-design bluespec-systemverilog processor-design vector-processor vlsi-design bluespec-systemverilog-language vlsi-cad
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Jan 11, 2021 - Bluespec
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
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Mar 3, 2024 - Jupyter Notebook
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
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Feb 25, 2021
A library for fast and optimized VLSI Computer-Aided-Design algorithms
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May 8, 2023 - Python
A binary decision diagram is a directed acyclic graph used to represent a Boolean function. The ROBDD is a canonical form, which means that given an identical ordering of input variables, equivalent Boolean functions will always reduce to the same ROBDD.
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Oct 2, 2022 - Jupyter Notebook
Contains vim dotfiles configured for verilog, C++ & some stuff for VLSI
vim vimrc vim-configs vim-plugin vim-configuration vim-plugins ide verilog vim-colorscheme sdc hdl vlsi verilog-hdl vimscript vlsi-physical-design upf vlsi-circuits verilog-project vlsi-design vlsi-cad
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Aug 14, 2021 - Vim Script
Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation
deep-neural-networks manufacturing intellectual-property hardware-security electronic-design-automation vlsi-cad
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Jan 30, 2021 - C++
Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay
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Dec 10, 2022 - Jupyter Notebook
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