timing-analysis

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

Easily benchmark PyTorch model FLOPs, latency, throughput, allocated gpu memory and energy consumption

This is a tutorial on standard digital design flow

Experimental Python tools for SANDD particle-detector waveform processing, timing and charge reconstruction, candidate selection, and ROOT visualization.

This repository contains code and data for "Tik-Tok: The Utility of Packet Timing in Website Fingerprinting Attacks" paper, published in PETS 2020.

Gate-level timing estimation toolkit

Unified audio and timing for Qur'an apps, developers, and researchers. A timestamps visualizer, editing tool and community-verified recitations dataset with word and letter timestamps

A NuGet that allows you to use a Azure DevOps Service Hook to track workitems changes in a simply and detailed way.

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

Evaluation Framework for Self-Suspending Task Systems

GG for Arduino is a serial console library. It also contains various functions for implementing the console, for example printf(). You can implement a command line interface on your Arduino and add your own commands. This library contains built-in commands that allow memory access and timing analysis.

Detect side channels with statistically rigorous methods.

Compiler backend from packing to bitstream generation.

Engineering notes and reproducible FPGA examples from real-world development, including RTL design, simulation, verification and debugging.

SerDes RTL design, verification using UVM and Physical design.

Static Timing Analyser (LIP6)

ASIC Physical Design of FIFO using Cadence Innovus | Floorplan → CTS → Routing → Timing & Power Analysis

Instruction cache artefacts in PQC timing evaluation on ARM Cortex-M4. A measurement harness and a false-positive leakage result traced to the STM32F4 ART accelerator. [Masters Project]