High throughput JPEG decoder in Verilog for FPGA
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Mar 5, 2022 - Verilog
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axi-stream
Here are 68 public repositories matching this topic...
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
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Jun 18, 2026 - SystemVerilog
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
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Mar 15, 2022 - Verilog
This project is designed to delay the output of the video stream in AXI-STREAM format.
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Jul 14, 2024 - Verilog
Tutorials or projects example to use Vivado 2019.2 and Vitis
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Oct 27, 2020 - VHDL
Various video processing projects will be shared here
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May 26, 2020 - Jupyter Notebook
Engineering notes and reproducible FPGA examples from real-world development, including RTL design, simulation, verification and debugging.
fpga zynq matlab rtl verilog chinese xilinx vivado digital-signal-processing rapidio engineering-notes axi-stream timing-analysis fpga-tutorial
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Jun 26, 2026 - Verilog
LASCON — A synthesizable SystemVerilog implementation of the NIST SP 800-232 Ascon lightweight cryptographic standard. Supports AEAD128, Hash256, XOF128, and CXOF128.
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Jul 19, 2026 - SystemVerilog
FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
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Dec 2, 2021 - SystemVerilog
Synchronous and Asynchronous FIFO with AXI interface
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Nov 20, 2019 - SystemVerilog
A one-position buffer compatible with AXI Stream interface
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May 23, 2023 - Tcl
FPGA benchmark of vectorized gradient descent on linear regression
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Mar 27, 2026 - VHDL
ReCONNECT: FPGA Optimized RTL-Native Parameterized Network-on-Chip
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Jun 1, 2026 - SystemVerilog
An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals
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Aug 10, 2020 - Tcl
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls axi-memory-mapped
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Nov 21, 2023 - TeX
FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
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Feb 20, 2023 - C
Parameterized output-stationary INT8 systolic MAC array in SystemVerilog for transformer Q/K/V/O and FFN matmuls. Milestone 1 of a 7-part CIM accelerator project.
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Jun 5, 2026 - SystemVerilog
Fast bwa-mem dna matching algor implemented in system verilog, fully synthesizable.
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Apr 9, 2022 - Stata
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