Network on Chip Simulator

A Chisel RTL generator for network-on-chip interconnects

Network on Chip Implementation written in SytemVerilog

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

Official read only mirror for

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

HLS for Networks-on-Chip

Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator

Cycle Accurate Network-on-Chip Simulator

DevJam 2020: In-game NOC boards

Network on Chip for MPSoC

whatever it means

Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research

System-on-Chip Interconnection Network - Simulation Environment (front-end)

openENOC is an open-source Ethernet-based NoC for scalable MPSoC systems, using Layer-2 frame switching to connect CPUs, accelerators and peripherals for crypto, AI and edge computing.

Sound and browser notification alerts for new Zabbix problems (Chrome MV3). Uses your open session, no token, nothing hardcoded. PT/EN/ES.

Fork of the gem5 simulator with Garnet2.0 and DSENT extensions

Azazel System: Cyber Scapegoat Gateway doctrine and tool family for delaying action, deception, and edge defense.