CoreFreq : CPU monitoring and tuning software designed for the 64-bit processors.

The Bug Reporting Repository for OutFox Alpha 4 LTS / V, Beta I Builds

SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus

🎮 PIU simulator for the GBA.

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA [FCCM 20]

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

DDR2 memory controller written in Verilog

u-boot DDR mods ~

A DNS full resolver and a stub command

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

An example of using Ramulator as memory model in a cycle-accurate SystemC Design

mirror of https://git.elphel.com/Elphel/eddr3

Xilinx PCIe to MIG DDR4 example designs and custom part data files

DDAL(Distributed Data Access Layer) is a simple solution to access database shard.

Unofficial script for playing KONAMI Amusement Game Station (Konaste/コナステ) games on Linux (and possibly other *nix OSes), using Wine

A modern website for DDR stepcharts. Think of them like guitar tabs, but for the songs's dance steps in the game.

573controller allows you to transform an Arduino Leonardo or Micro into various 573 music game controllers

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

DDR5 SPD EEPROM recovery tools.