一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

HDL support for VS Code

Bluespec SystemVerilog extension for VS Code

Bluespec System Verilog language extension for Visual Studio Code

Bluespec SystemVerilog Package for Sublime Text

Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.

Forth CPU J1 in Bluespec SystemVerilog (BSV)

CMake modules for building Bluespec targets

Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)

To toy around with Bluespec-SystemVerilog and my Basys3 board

Aetheron is a minimal RISC-V SoC using a TileLink-lite interconnect and basic peripherals that can run bare metal C programs

🐋Docker for Bluespec SystemVerilog (BSV) on WSL2, compatible with WangXuan95/BSV_Tutorial_cn.

Bluespec implementation of PG routing algorithm on a network on chip running a SMIPS

Implementação do protocolo TCP para a disciplina de Redes de Computadores da Universidade Federal de São Carlos - UFSCar

Specula is a Dual-Issue, Out-of-Order RISC-V RV32I core featuring basic Dynamic Scheduling and Register Renaming. Designed for simulation (WIP)

A collection of activation functions implemented in Bluespec for integration with hardware designs, ensuring IEEE 754 compliance

Bluespec System Verilog syntax highlighting for Notepad++

FSM coding styles in BSV

Wishbone/Bluespec Systemverilog Transactors

Hardware implementation of floating point unit (IEEE-754 compliant) for RISC-V architecture