iverilog

Here are 143 public repositories matching this topic...

mshr-h / vscode-verilog-hdl-support

Verilog/SystemVerilog support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Jul 25, 2026
TypeScript

TimRudy / ice-chips-verilog

Star

IceChips is a library of all common discrete logic devices in Verilog

fpga open-hardware eda digital-logic icestorm iverilog logic-circuit verilog-components 7400

Updated Jun 10, 2026
Verilog

ashishrana160796 / verilog-starter-tutorials

Star

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

practice embedded-systems verilog up-for-grabs circuit switches beginner-friendly logic-gates hdl verilog-hdl iverilog verilog-snippets verilog-programs verilog-project

Updated Nov 25, 2020
Verilog

TheSUPERCD / 8bit_MicroComputer_Verilog

Sponsor

Star

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

verilog verilog-hdl 8bit iverilog verilog-project ben-eater verilog-code ben-eaters-cpu

Updated Nov 30, 2022
Verilog

JeffDeCola / my-verilog-examples

Star

A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated May 19, 2026
Verilog

sgherbst / svreal

Star

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

TimRudy / uart-verilog

Star

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

fpga open-hardware eda digital-logic hardware-designs serialport icestorm uart-verilog iverilog verilog-components uart-interface

Updated Oct 3, 2025
Verilog

Essenceia / ethernet-physical-layer

Star

RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

c fpga rtl verilog ethernet iverilog vpi pcs 10gbase-r 40gbase-r

Updated Jan 2, 2024
Tcl

bjwanneng / veriflow-cc

Star

VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.