Must-have verilog systemverilog modules

A simple, basic, formally verified UART controller

A simple implementation of a UART modem in Verilog.

Interface Protocol in Verilog

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

☎️ UART Communication Implementation in Verilog HDL

Displaying images taken from an OV7670/laptop camera

Universal Asynchronous Receiver Transmitter

A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX

Transferring data from SPI to UART using BMP280 sensor with Verilog

UART implementation using Verilog HDL

UART Tx implemented in SystemVerilog from scratch.

Basys 3 UART Tx for COMPE470L class

Verilog Modeling of UART Tx and Rx

This project implements a UART-controlled processing unit with dual clock domains for UART communication and datapath operations. A state machine decodes serial commands to control the datapath, enabling ALU operations, register file access, and data transmission. It's designed for embedded systems and educational purposes.

Single-cycle MIPS-based processor architecture, designed as the final project for the Laboratory of Computer Architecture and Organization course and later enhanced for both Laboratory of Operational Systems and Laboratory of Computer Networks courses.