ASIC implementation flow infrastructure, successor to OpenLane
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Jul 24, 2026 - Python
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librelane
Here are 19 public repositories matching this topic...
Firmware-driven dual-die RV32 chiplet SoC with GCC/ISS co-verification, DMA/AES offload, UPF 4.0 low-power intent, async CDC, real UVM, formal, and open-source coverage.
riscv systemverilog cdc formal-verification low-power verilator upf design-verification ucie librelane
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Jul 18, 2026 - SystemVerilog
Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host interface, and fused streaming datapath. Validated on chest X-ray pneumonia detection. Silicon Sprint 2026 — AUC.
tapeout systolic-arrays npu openroad edge-ai asic-design medical-ai int8-quantization digital-ic-design librelane rtl-to-gdsii skywater-130nm
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May 24, 2026 - Verilog
AI/LLM-assisted circuit design using opensource tools
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May 18, 2026 - Python
High-Efficiency 16-bit BFloat16 Multiply-Accumulate (MAC) Unit for ML Acceleration. Verified for SkyWater 130nm (TinyTapeout 07). Includes FP32 accumulation and streaming I/O.
machine-learning asic rtl verilog systemverilog hardware-acceleration cocotb bfloat16 openlane sky130 fp32 tinytapeout librelane
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Feb 16, 2026 - Python
Chipathon 2026 workshop padring fork of wafer-space/gf180mcu-project-template - adds a workshop slot mirroring JuanMoya/padring_gf180 as a native LibreLane slot.
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Apr 24, 2026 - Python
Simple Systolic array implementation
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May 15, 2026 - Verilog
Chipathon GF180MCU LibreLane examples: 5 hands-on notebooks (counter bare-block, chip-top with macro, workshop slot use, multi-macro counter+ALU) for the chipathon-2026-gf180mcu-padring fork.
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Apr 26, 2026 - Jupyter Notebook
Browser cockpit & IDE for the LibreLane RTL-to-GDS chip flow — run, verify, and explore silicon flows without living in a terminal.
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Jul 19, 2026 - Python
Open-source ASIC flow laboratory focused on LibreLane, OpenROAD, Yosys, and open silicon workflows.
opensource asic hardware eda rtl vlsi yosys digital-design silicon gdsii physical-design openroad openlane sky130 librelane
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Jun 13, 2026
Beginner-friendly, Docker-based starter kit for designing a GF180MCU chip from RTL to a manufacturable GDSII — simulate, verify, and harden a working example, then make it yours and submit it to a wafer.space shuttle.
asic docker-compose eda gds open-source-hardware systemverilog-hdl gdsii asic-verification tapeout openroad gf180mcu open-source-silicon gf180 librelane wafer-space tepeout-tools
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Jul 3, 2026 - SystemVerilog
1x2 SKY130 Tiny Tapeout game design with 640x480 VGA, QSPI PSRAM, dual controllers, cocotb verification, and RTL-to-GDS signoff.
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Jul 24, 2026 - Verilog
Area-optimized 1x1 SKY130 Tiny Tapeout game design with 640x480 VGA, QSPI PSRAM, dual controllers, and RTL/gate-level verification.
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Jul 24, 2026 - Python
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