Awesome ASIC design verification

IC implementation of Systolic Array for TPU

VIP for AXI Protocol

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …

Quasar 2.0: Chisel equivalent of SweRV-EL2

A custom AI chip to be taped out soon!

Hdl is a tool for easing the work with hardware description languages.

BDD Gherkin implementation in native SystemVerilog, based on UVM.

The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.

Application Specific Integrated Circuit(ASIC)

VIP for I2C

.NET Scripting Engine for Cadence(R) Indago(R) Interactive Verification Enviroment

Made Million Instruction Per Second Processor

UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)

Laboraory manuals and Discussion

End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.

TCL examples from the Clif Flynt's classic

VHDL implementation of an "asynchronous" FIFO with 64 positions of 8-bit words. Features dual clock domains (wr_clk, rd_clk), asynchronous reset, status signals (empty, full, almost empty/full, error), testbench, synthesis scripts, and timing/power/area reports.