OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

Python packages providing a library for Verification Stimulus and Coverage

Constrained random stimuli generation for C++ and SystemC

A Python package for creating and solving constrained randomization problems.

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)

SystemVerilog memory verification using constrained-random stimulus, mailboxes, monitors, and a reference checker.

Public portfolio of APB4 and AXI4 verification methodology using SystemVerilog, UVM, SVA and coverage.

Explorations in Uniform Sampling of SMT2 Constraints

Multi-state Mealy/Moore FSM in SystemVerilog with SVA assertions, constrained-random testbenches, and functional coverage — synthesizable on Xilinx FPGAs

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

Learning project: parameterized FIFO RTL with an evolving SystemVerilog/UVM verification environment.

SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

Dual-clock asynchronous FIFO in SystemVerilog with layered verification: constrained-random testbench, functional coverage, SVA, SymbiYosys formal spec

Backpressure-safe 1-stage valid-ready pipeline in SystemVerilog with constrained-random verification, assertions (SVA), and waveform validation.

A personal SystemVerilog playground of RTL design and verification experiments — arbiters, ALUs (conventional/class-based/UVM), multipliers, FSM controllers, and floating-point classes — plus a 17-demo gallery of language 'gotchas' and timing-window traps, each with self-checking testbenches, assertions, coverage, and Questa run scripts.

UVM-based verification portfolio for APB, AXI, I2C, SPI, and UART protocols. Class-based testbenches with sequence library, reference model, dual TLM-FIFO scoreboard, functional coverage (uvm_subscriber), SVA assertions, and Makefile/TCL build flow.

Constrained-random verification and functional coverage for AI agents, with seeded bug reproduction