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#

half-adder

Here are 32 public repositories matching this topic...

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

  • Updated Aug 24, 2024
  • Verilog

Digital Design laboratory project demonstrating binary arithmetic circuits, including Half Adder, Full Adder, Half Subtractor, Full Subtractor, with interactive NI Multisim simulations, truth tables, and logical equation analysis (Logic Design, UNIWA).

  • Updated Feb 21, 2026

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