Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

Basic pytorch implementation of NAC/NALU from Neural Arithmetic Logic Units paper by trask et.al

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

Computer built from the ground up on top of own CPU, while compiler and assembler for it implemented in Rust language

Version 2 of my Crazy Small CPU

Payu ALU service client

Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu

MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Solutions for all levels of the NandGame.

8-bit combinational ALU built from scratch with 3,488 CMOS transistors (KiCad + SPICE + Logisim + 1.24M tests

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

The Read Origin Protocol (ROP) is a computational protocol that aims to discover the source of all reads, including those originating from repeat sequences, recombinant B and T cell receptors, and microbial communities.

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

ALU Verilog Project calculate add, subtract, increment, decrement, multiply

Design your own CPU, Operating system, and Compiler (Maintainer: Emin Ghuliev)

Simple As Possible (SAP) 1 Computer Design in Logisim

Genotyping of segregating mobile elements insertions