💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

Database of CPU Opcodes

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

Advanced Matrix Extensions (AMX) Guide

Assembly program with the MIPS instruction set

XCrypto: a cryptographic ISE for RISC-V

UME::SIMD A library for explicit simd vectorization.

AluVM: RISC functional machine base implementation

RISC-V Assembly code assembler package for Python.

🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.

HF-RISC SoC

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

SCARV: a side-channel hardened RISC-V platform

💾 The LC3 virtual machine

Super scalar Processor design

64-bit RISC CPU Architecture

Kite: Architecture Simulator for RISC-V Instruction Set

Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.

RISC-V Assembly code assembler package for Python.