Teaching Materials for Dr. Waleed A. Yousef

Automatically interpret and validate nested natural logic arguments based on rules of inference and propositional logic

All the homeworks, studies and projects I've done at Metu-CENG

Water Level Meter

EventNext is logic interface design actors components for .net core

Circuit Builder Desktop Application (like mmlogic) made with Electron + React Typescript. Compatible with Windows, Mac and Linux.

Logic Minimization in Python

All the homeworks, testers and projects done at METU-CENG

All the homeworks, testers and projects done at Marmara University, Computer Science & Engineering

SystemVerilog examples for a digital design course

As an Ignite Coder, solved numerous problems using C programming, demonstrating expertise in algorithms, problem-solving, and efficient coding for technical challenges.

ELVE : ELVE Logic Visualization Engine

This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.

Projects of a CSE student at Marmara University

A collection of digital logic circuits

Automated conversion from CHP to PRS using syntax-directed translation

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog

Windows application for designing and simulating digital logic circuits, written in C++ using CMU graphics library.

A puzzle game for iOS.