Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

Behavioral architecture of a read/write cycle controller for a DRAM chip.

This repository contains a Verilog-based design and testbench for modeling a simple asynchronous RAM module. It is designed to simulate basic memory read/write behavior without the use of a clock, allowing learners and engineers to better understand low-level memory interactions.

Repository with shell scripts, OS installation tasks, assembly language, and HDL files for the Computer Architecture and Operating Systems (ACSO) course at Escuela Colombiana de Ingeniería.

PESU Sem 3: Mini project for Digital Design and Computer Organization

SRAM Collection – Parameterized Verilog Modules for Single Port SRAM (sync/async read), Pseudo Dual Port SRAM (sync read), and True Dual Port SRAM – all parameterized, fully synthesizable, and demo’d with testbenches and waveforms.