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/RTL : VerilogHDL RTL source codes for iverilog simulation
Current Progress
✅ Rhealstone switch, preempt benchmark
📝 Full function support for FreeRTOS and verification with other 4 Rhealstone benchmarks.
Overview
This repository is about implementing FreeRTOS Kernel on 8-stage pipelined bare-metal RISC-V processor from RV-IM100.
FreeRTOS: An open-source real-time operating system kernel providing preemptive scheduling, software timers, and inter-task communication for resource-constrained embedded systems.
RV-IM100:
Design guidelines and performance analysis for 10 RISC-V 5- to 8-stage pipeline variants based on basic_RV32S and IMA_make_RV64, covering ISA extension scaling, pipeline-depth sweep, and 100 MHz(125) timing closure on Artix-7 FPGA.
To make the fully working computing system, we've also implemented HDMI display output interface with PS/2 keyboard input interface.
To verify the FreeRTOS implementation, we've benchmarked with Rhealstone within our original shell program.
Rhealstone:
A benchmark suite for evaluating real-time operating system performance, measuring key metrics such as task switching time, preemption time, interrupt latency, semaphore shuffling, message passing, and deadlock breaking.
We couldn't fine the original source code of Rhealstone, so we've ported RTEMS Rhealstone to FreeRTOS.
Architecture
Core Architecture
RV64IM72F_8SP Core Architecture block diagram
IF-IO-ID-EXR-EX-BR-MEM-WB : 8-Stage Pipeline
We've revised several modules for FreeRTOS support.
trap-exception logic modules for ECALL & timer tick interaction from FreeRTOS.
FreeRTOS porting on 8-stage pipelined RISC-V CPU with HDMI and keyboards
RV64IM72F_8SP Core Architecture block diagram
72F8SP_SoC Architecture block diagram
