1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _LINUX_CORESIGHT_H
7#define _LINUX_CORESIGHT_H
8
9#include <linux/amba/bus.h>
10#include <linux/clk.h>
11#include <linux/device.h>
12#include <linux/io.h>
13#include <linux/perf_event.h>
14#include <linux/sched.h>
15#include <linux/platform_device.h>
16
17/* Peripheral id registers (0xFD0-0xFEC) */
18#define CORESIGHT_PERIPHIDR4 0xfd0
19#define CORESIGHT_PERIPHIDR5 0xfd4
20#define CORESIGHT_PERIPHIDR6 0xfd8
21#define CORESIGHT_PERIPHIDR7 0xfdC
22#define CORESIGHT_PERIPHIDR0 0xfe0
23#define CORESIGHT_PERIPHIDR1 0xfe4
24#define CORESIGHT_PERIPHIDR2 0xfe8
25#define CORESIGHT_PERIPHIDR3 0xfeC
26/* Component id registers (0xFF0-0xFFC) */
27#define CORESIGHT_COMPIDR0 0xff0
28#define CORESIGHT_COMPIDR1 0xff4
29#define CORESIGHT_COMPIDR2 0xff8
30#define CORESIGHT_COMPIDR3 0xffC
31
32#define ETM_ARCH_V3_3 0x23
33#define ETM_ARCH_V3_5 0x25
34#define PFT_ARCH_V1_0 0x30
35#define PFT_ARCH_V1_1 0x31
36
37#define CORESIGHT_UNLOCK 0xc5acce55
38
39extern const struct bus_type coresight_bustype;
40
41enum coresight_dev_type {
42 CORESIGHT_DEV_TYPE_SINK,
43 CORESIGHT_DEV_TYPE_LINK,
44 CORESIGHT_DEV_TYPE_LINKSINK,
45 CORESIGHT_DEV_TYPE_SOURCE,
46 CORESIGHT_DEV_TYPE_HELPER,
47 CORESIGHT_DEV_TYPE_MAX
48};
49
50enum coresight_dev_subtype_sink {
51 CORESIGHT_DEV_SUBTYPE_SINK_DUMMY,
52 CORESIGHT_DEV_SUBTYPE_SINK_PORT,
53 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
54 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
55 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
56};
57
58enum coresight_dev_subtype_link {
59 CORESIGHT_DEV_SUBTYPE_LINK_MERG,
60 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
61 CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
62};
63
64enum coresight_dev_subtype_source {
65 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
66 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
67 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
68 CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM,
69 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS,
70};
71
72enum coresight_dev_subtype_helper {
73 CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
74 CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI,
75 CORESIGHT_DEV_SUBTYPE_HELPER_CTCU,
76};
77
78/**
79 * union coresight_dev_subtype - further characterisation of a type
80 * @sink_subtype: type of sink this component is, as defined
81 * by @coresight_dev_subtype_sink.
82 * @link_subtype: type of link this component is, as defined
83 * by @coresight_dev_subtype_link.
84 * @source_subtype: type of source this component is, as defined
85 * by @coresight_dev_subtype_source.
86 * @helper_subtype: type of helper this component is, as defined
87 * by @coresight_dev_subtype_helper.
88 */
89union coresight_dev_subtype {
90 /* We have some devices which acts as LINK and SINK */
91 struct {
92 enum coresight_dev_subtype_sink sink_subtype;
93 enum coresight_dev_subtype_link link_subtype;
94 };
95 enum coresight_dev_subtype_source source_subtype;
96 enum coresight_dev_subtype_helper helper_subtype;
97};
98
99/**
100 * struct coresight_platform_data - data harvested from the firmware
101 * specification.
102 *
103 * @nr_inconns: Number of elements for the input connections.
104 * @nr_outconns: Number of elements for the output connections.
105 * @out_conns: Array of nr_outconns pointers to connections from this
106 * component.
107 * @in_conns: Sparse array of pointers to input connections. Sparse
108 * because the source device owns the connection so when it's
109 * unloaded the connection leaves an empty slot.
110 */
111struct coresight_platform_data {
112 int nr_inconns;
113 int nr_outconns;
114 struct coresight_connection **out_conns;
115 struct coresight_connection **in_conns;
116};
117
118/**
119 * struct csdev_access - Abstraction of a CoreSight device access.
120 *
121 * @io_mem : True if the device has memory mapped I/O
122 * @base : When io_mem == true, base address of the component
123 * @read : Read from the given "offset" of the given instance.
124 * @write : Write "val" to the given "offset".
125 */
126struct csdev_access {
127 bool io_mem;
128 union {
129 void __iomem *base;
130 struct {
131 u64 (*read)(u32 offset, bool relaxed, bool _64bit);
132 void (*write)(u64 val, u32 offset, bool relaxed,
133 bool _64bit);
134 };
135 };
136};
137
138#define CSDEV_ACCESS_IOMEM(_addr) \
139 ((struct csdev_access) { \
140 .io_mem = true, \
141 .base = (_addr), \
142 })
143
144/**
145 * struct coresight_desc - description of a component required from drivers
146 * @type: as defined by @coresight_dev_type.
147 * @subtype: as defined by @coresight_dev_subtype.
148 * @ops: generic operations for this component, as defined
149 * by @coresight_ops.
150 * @pdata: platform data collected from DT.
151 * @dev: The device entity associated to this component.
152 * @groups: operations specific to this component. These will end up
153 * in the component's sysfs sub-directory.
154 * @name: name for the coresight device, also shown under sysfs.
155 * @access: Describe access to the device
156 */
157struct coresight_desc {
158 enum coresight_dev_type type;
159 union coresight_dev_subtype subtype;
160 const struct coresight_ops *ops;
161 struct coresight_platform_data *pdata;
162 struct device *dev;
163 const struct attribute_group **groups;
164 const char *name;
165 struct csdev_access access;
166};
167
168/**
169 * struct coresight_connection - representation of a single connection
170 * @src_port: a connection's output port number.
171 * @dest_port: destination's input port number @src_port is connected to.
172 * @dest_fwnode: destination component's fwnode handle.
173 * @dest_dev: a @coresight_device representation of the component
174 connected to @src_port. NULL until the device is created
175 * @link: Representation of the connection as a sysfs link.
176 * @filter_src_fwnode: filter source component's fwnode handle.
177 * @filter_src_dev: a @coresight_device representation of the component that
178 needs to be filtered.
179 *
180 * The full connection structure looks like this, where in_conns store
181 * references to same connection as the source device's out_conns.
182 *
183 * +-----------------------------+ +-----------------------------+
184 * |coresight_device | |coresight_connection |
185 * |-----------------------------| |-----------------------------|
186 * | | | |
187 * | | | dest_dev*|<--
188 * |pdata->out_conns[nr_outconns]|<->|src_dev* | |
189 * | | | | |
190 * +-----------------------------+ +-----------------------------+ |
191 * |
192 * +-----------------------------+ |
193 * |coresight_device | |
194 * |------------------------------ |
195 * | | |
196 * | pdata->in_conns[nr_inconns]|<--
197 * | |
198 * +-----------------------------+
199 */
200struct coresight_connection {
201 int src_port;
202 int dest_port;
203 struct fwnode_handle *dest_fwnode;
204 struct coresight_device *dest_dev;
205 struct coresight_sysfs_link *link;
206 struct coresight_device *src_dev;
207 struct fwnode_handle *filter_src_fwnode;
208 struct coresight_device *filter_src_dev;
209 int src_refcnt;
210 int dest_refcnt;
211};
212
213/**
214 * struct coresight_sysfs_link - representation of a connection in sysfs.
215 * @orig: Originating (master) coresight device for the link.
216 * @orig_name: Name to use for the link orig->target.
217 * @target: Target (slave) coresight device for the link.
218 * @target_name: Name to use for the link target->orig.
219 */
220struct coresight_sysfs_link {
221 struct coresight_device *orig;
222 const char *orig_name;
223 struct coresight_device *target;
224 const char *target_name;
225};
226
227/* architecturally we have 128 IDs some of which are reserved */
228#define CORESIGHT_TRACE_IDS_MAX 128
229
230/**
231 * Trace ID map.
232 *
233 * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs.
234 * Initialised so that the reserved IDs are permanently marked as
235 * in use.
236 * @perf_cs_etm_session_active: Number of Perf sessions using this ID map.
237 */
238struct coresight_trace_id_map {
239 DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX);
240 atomic_t __percpu *cpu_map;
241 atomic_t perf_cs_etm_session_active;
242 raw_spinlock_t lock;
243};
244
245/**
246 * struct coresight_device - representation of a device as used by the framework
247 * @pdata: Platform data with device connections associated to this device.
248 * @type: as defined by @coresight_dev_type.
249 * @subtype: as defined by @coresight_dev_subtype.
250 * @ops: generic operations for this component, as defined
251 * by @coresight_ops.
252 * @access: Device i/o access abstraction for this device.
253 * @dev: The device entity associated to this component.
254 * @mode: This tracer's mode, i.e sysFS, Perf or disabled. This is
255 * actually an 'enum cs_mode', but is stored in an atomic type.
256 * This is always accessed through local_read() and local_set(),
257 * but wherever it's done from within the Coresight device's lock,
258 * a non-atomic read would also work. This is the main point of
259 * synchronisation between code happening inside the sysfs mode's
260 * coresight_mutex and outside when running in Perf mode. A compare
261 * and exchange swap is done to atomically claim one mode or the
262 * other.
263 * @refcnt: keep track of what is in use. Only access this outside of the
264 * device's spinlock when the coresight_mutex held and mode ==
265 * CS_MODE_SYSFS. Otherwise it must be accessed from inside the
266 * spinlock.
267 * @orphan: true if the component has connections that haven't been linked.
268 * @sysfs_sink_activated: 'true' when a sink has been selected for use via sysfs
269 * by writing a 1 to the 'enable_sink' file. A sink can be
270 * activated but not yet enabled. Enabling for a _sink_ happens
271 * when a source has been selected and a path is enabled from
272 * source to that sink. A sink can also become enabled but not
273 * activated if it's used via Perf.
274 * @ea: Device attribute for sink representation under PMU directory.
275 * @def_sink: cached reference to default sink found for this device.
276 * @nr_links: number of sysfs links created to other components from this
277 * device. These will appear in the "connections" group.
278 * @has_conns_grp: Have added a "connections" group for sysfs links.
279 * @feature_csdev_list: List of complex feature programming added to the device.
280 * @config_csdev_list: List of system configurations added to the device.
281 * @cscfg_csdev_lock: Protect the lists of configurations and features.
282 * @active_cscfg_ctxt: Context information for current active system configuration.
283 */
284struct coresight_device {
285 struct coresight_platform_data *pdata;
286 enum coresight_dev_type type;
287 union coresight_dev_subtype subtype;
288 const struct coresight_ops *ops;
289 struct csdev_access access;
290 struct device dev;
291 local_t mode;
292 int refcnt;
293 bool orphan;
294 /* sink specific fields */
295 bool sysfs_sink_activated;
296 struct dev_ext_attribute *ea;
297 struct coresight_device *def_sink;
298 struct coresight_trace_id_map perf_sink_id_map;
299 /* sysfs links between components */
300 int nr_links;
301 bool has_conns_grp;
302 /* system configuration and feature lists */
303 struct list_head feature_csdev_list;
304 struct list_head config_csdev_list;
305 raw_spinlock_t cscfg_csdev_lock;
306 void *active_cscfg_ctxt;
307};
308
309/*
310 * coresight_dev_list - Mapping for devices to "name" index for device
311 * names.
312 *
313 * @nr_idx: Number of entries already allocated.
314 * @pfx: Prefix pattern for device name.
315 * @fwnode_list: Array of fwnode_handles associated with each allocated
316 * index, upto nr_idx entries.
317 */
318struct coresight_dev_list {
319 int nr_idx;
320 const char *pfx;
321 struct fwnode_handle **fwnode_list;
322};
323
324#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
325static struct coresight_dev_list (var) = { \
326 .pfx = dev_pfx, \
327 .nr_idx = 0, \
328 .fwnode_list = NULL, \
329}
330
331#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
332
333/**
334 * struct coresight_path - data needed by enable/disable path
335 * @path_list: path from source to sink.
336 * @trace_id: trace_id of the whole path.
337 */
338struct coresight_path {
339 struct list_head path_list;
340 u8 trace_id;
341};
342
343enum cs_mode {
344 CS_MODE_DISABLED,
345 CS_MODE_SYSFS,
346 CS_MODE_PERF,
347};
348
349#define coresight_ops(csdev) csdev->ops
350#define source_ops(csdev) csdev->ops->source_ops
351#define sink_ops(csdev) csdev->ops->sink_ops
352#define link_ops(csdev) csdev->ops->link_ops
353#define helper_ops(csdev) csdev->ops->helper_ops
354#define ect_ops(csdev) csdev->ops->ect_ops
355#define panic_ops(csdev) csdev->ops->panic_ops
356
357/**
358 * struct coresight_ops_sink - basic operations for a sink
359 * Operations available for sinks
360 * @enable: enables the sink.
361 * @disable: disables the sink.
362 * @alloc_buffer: initialises perf's ring buffer for trace collection.
363 * @free_buffer: release memory allocated in @get_config.
364 * @update_buffer: update buffer pointers after a trace session.
365 */
366struct coresight_ops_sink {
367 int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
368 void *data);
369 int (*disable)(struct coresight_device *csdev);
370 void *(*alloc_buffer)(struct coresight_device *csdev,
371 struct perf_event *event, void **pages,
372 int nr_pages, bool overwrite);
373 void (*free_buffer)(void *config);
374 unsigned long (*update_buffer)(struct coresight_device *csdev,
375 struct perf_output_handle *handle,
376 void *sink_config);
377};
378
379/**
380 * struct coresight_ops_link - basic operations for a link
381 * Operations available for links.
382 * @enable: enables flow between iport and oport.
383 * @disable: disables flow between iport and oport.
384 */
385struct coresight_ops_link {
386 int (*enable)(struct coresight_device *csdev,
387 struct coresight_connection *in,
388 struct coresight_connection *out);
389 void (*disable)(struct coresight_device *csdev,
390 struct coresight_connection *in,
391 struct coresight_connection *out);
392};
393
394/**
395 * struct coresight_ops_source - basic operations for a source
396 * Operations available for sources.
397 * @cpu_id: returns the value of the CPU number this component
398 * is associated to.
399 * @enable: enables tracing for a source.
400 * @disable: disables tracing for a source.
401 * @resume_perf: resumes tracing for a source in perf session.
402 * @pause_perf: pauses tracing for a source in perf session.
403 */
404struct coresight_ops_source {
405 int (*cpu_id)(struct coresight_device *csdev);
406 int (*enable)(struct coresight_device *csdev, struct perf_event *event,
407 enum cs_mode mode, struct coresight_path *path);
408 void (*disable)(struct coresight_device *csdev,
409 struct perf_event *event);
410 int (*resume_perf)(struct coresight_device *csdev);
411 void (*pause_perf)(struct coresight_device *csdev);
412};
413
414/**
415 * struct coresight_ops_helper - Operations for a helper device.
416 *
417 * All operations could pass in a device specific data, which could
418 * help the helper device to determine what to do.
419 *
420 * @enable : Enable the device
421 * @disable : Disable the device
422 */
423struct coresight_ops_helper {
424 int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
425 void *data);
426 int (*disable)(struct coresight_device *csdev, void *data);
427};
428
429
430/**
431 * struct coresight_ops_panic - Generic device ops for panic handing
432 *
433 * @sync : Sync the device register state/trace data
434 */
435struct coresight_ops_panic {
436 int (*sync)(struct coresight_device *csdev);
437};
438
439struct coresight_ops {
440 int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
441 struct coresight_device *sink);
442 const struct coresight_ops_sink *sink_ops;
443 const struct coresight_ops_link *link_ops;
444 const struct coresight_ops_source *source_ops;
445 const struct coresight_ops_helper *helper_ops;
446 const struct coresight_ops_panic *panic_ops;
447};
448
449static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
450 u32 offset)
451{
452 if (likely(csa->io_mem))
453 return readl_relaxed(csa->base + offset);
454
455 return csa->read(offset, true, false);
456}
457
458#define CORESIGHT_CIDRn(i) (0xFF0 + ((i) * 4))
459
460static inline u32 coresight_get_cid(void __iomem *base)
461{
462 u32 i, cid = 0;
463
464 for (i = 0; i < 4; i++)
465 cid |= readl(addr: base + CORESIGHT_CIDRn(i)) << (i * 8);
466
467 return cid;
468}
469
470static inline bool is_coresight_device(void __iomem *base)
471{
472 u32 cid = coresight_get_cid(base);
473
474 return cid == CORESIGHT_CID;
475}
476
477/*
478 * Attempt to find and enable "APB clock" for the given device
479 *
480 * Returns:
481 *
482 * clk - Clock is found and enabled
483 * NULL - clock is not found
484 * ERROR - Clock is found but failed to enable
485 */
486static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev)
487{
488 struct clk *pclk;
489 int ret;
490
491 pclk = clk_get(dev, id: "apb_pclk");
492 if (IS_ERR(ptr: pclk)) {
493 pclk = clk_get(dev, id: "apb");
494 if (IS_ERR(ptr: pclk))
495 return NULL;
496 }
497
498 ret = clk_prepare_enable(clk: pclk);
499 if (ret) {
500 clk_put(clk: pclk);
501 return ERR_PTR(error: ret);
502 }
503 return pclk;
504}
505
506#define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4))
507
508static inline u32 coresight_get_pid(struct csdev_access *csa)
509{
510 u32 i, pid = 0;
511
512 for (i = 0; i < 4; i++)
513 pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8);
514
515 return pid;
516}
517
518static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa,
519 u32 lo_offset, u32 hi_offset)
520{
521 if (likely(csa->io_mem)) {
522 return readl_relaxed(csa->base + lo_offset) |
523 ((u64)readl_relaxed(csa->base + hi_offset) << 32);
524 }
525
526 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32);
527}
528
529static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val,
530 u32 lo_offset, u32 hi_offset)
531{
532 if (likely(csa->io_mem)) {
533 writel_relaxed((u32)val, csa->base + lo_offset);
534 writel_relaxed((u32)(val >> 32), csa->base + hi_offset);
535 } else {
536 csa->write((u32)val, lo_offset, true, false);
537 csa->write((u32)(val >> 32), hi_offset, true, false);
538 }
539}
540
541static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
542{
543 if (likely(csa->io_mem))
544 return readl(addr: csa->base + offset);
545
546 return csa->read(offset, false, false);
547}
548
549static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
550 u32 val, u32 offset)
551{
552 if (likely(csa->io_mem))
553 writel_relaxed(val, csa->base + offset);
554 else
555 csa->write(val, offset, true, false);
556}
557
558static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
559{
560 if (likely(csa->io_mem))
561 writel(val, addr: csa->base + offset);
562 else
563 csa->write(val, offset, false, false);
564}
565
566#ifdef CONFIG_64BIT
567
568static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
569 u32 offset)
570{
571 if (likely(csa->io_mem))
572 return readq_relaxed(csa->base + offset);
573
574 return csa->read(offset, true, true);
575}
576
577static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
578{
579 if (likely(csa->io_mem))
580 return readq(addr: csa->base + offset);
581
582 return csa->read(offset, false, true);
583}
584
585static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
586 u64 val, u32 offset)
587{
588 if (likely(csa->io_mem))
589 writeq_relaxed(val, csa->base + offset);
590 else
591 csa->write(val, offset, true, true);
592}
593
594static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
595{
596 if (likely(csa->io_mem))
597 writeq(val, addr: csa->base + offset);
598 else
599 csa->write(val, offset, false, true);
600}
601
602#else /* !CONFIG_64BIT */
603
604static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
605 u32 offset)
606{
607 WARN_ON(1);
608 return 0;
609}
610
611static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
612{
613 WARN_ON(1);
614 return 0;
615}
616
617static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
618 u64 val, u32 offset)
619{
620 WARN_ON(1);
621}
622
623static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
624{
625 WARN_ON(1);
626}
627#endif /* CONFIG_64BIT */
628
629static inline bool coresight_is_device_source(struct coresight_device *csdev)
630{
631 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE);
632}
633
634static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
635{
636 return csdev && coresight_is_device_source(csdev) &&
637 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
638}
639
640static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
641{
642 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
643 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
644}
645
646/*
647 * Atomically try to take the device and set a new mode. Returns true on
648 * success, false if the device is already taken by someone else.
649 */
650static inline bool coresight_take_mode(struct coresight_device *csdev,
651 enum cs_mode new_mode)
652{
653 return local_cmpxchg(l: &csdev->mode, old: CS_MODE_DISABLED, new: new_mode) ==
654 CS_MODE_DISABLED;
655}
656
657static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev)
658{
659 return local_read(&csdev->mode);
660}
661
662static inline void coresight_set_mode(struct coresight_device *csdev,
663 enum cs_mode new_mode)
664{
665 enum cs_mode current_mode = coresight_get_mode(csdev);
666
667 /*
668 * Changing to a new mode must be done from an already disabled state
669 * unless it's synchronized with coresight_take_mode(). Otherwise the
670 * device is already in use and signifies a locking issue.
671 */
672 WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED &&
673 current_mode != new_mode, "Device already in use\n");
674
675 local_set(&csdev->mode, new_mode);
676}
677
678struct coresight_device *coresight_register(struct coresight_desc *desc);
679void coresight_unregister(struct coresight_device *csdev);
680int coresight_enable_sysfs(struct coresight_device *csdev);
681void coresight_disable_sysfs(struct coresight_device *csdev);
682int coresight_timeout(struct csdev_access *csa, u32 offset, int position, int value);
683typedef void (*coresight_timeout_cb_t) (struct csdev_access *, u32, int, int);
684int coresight_timeout_action(struct csdev_access *csa, u32 offset, int position, int value,
685 coresight_timeout_cb_t cb);
686int coresight_claim_device(struct coresight_device *csdev);
687int coresight_claim_device_unlocked(struct coresight_device *csdev);
688
689int coresight_claim_device(struct coresight_device *csdev);
690int coresight_claim_device_unlocked(struct coresight_device *csdev);
691void coresight_clear_self_claim_tag(struct csdev_access *csa);
692void coresight_clear_self_claim_tag_unlocked(struct csdev_access *csa);
693void coresight_disclaim_device(struct coresight_device *csdev);
694void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
695char *coresight_alloc_device_name(struct coresight_dev_list *devs,
696 struct device *dev);
697
698bool coresight_loses_context_with_cpu(struct device *dev);
699
700u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
701u32 coresight_read32(struct coresight_device *csdev, u32 offset);
702void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
703void coresight_relaxed_write32(struct coresight_device *csdev,
704 u32 val, u32 offset);
705u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
706u64 coresight_read64(struct coresight_device *csdev, u32 offset);
707void coresight_relaxed_write64(struct coresight_device *csdev,
708 u64 val, u32 offset);
709void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
710
711int coresight_get_cpu(struct device *dev);
712int coresight_get_static_trace_id(struct device *dev, u32 *id);
713
714struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
715struct coresight_connection *
716coresight_add_out_conn(struct device *dev,
717 struct coresight_platform_data *pdata,
718 const struct coresight_connection *new_conn);
719int coresight_add_in_conn(struct coresight_connection *conn);
720struct coresight_device *
721coresight_find_input_type(struct coresight_platform_data *pdata,
722 enum coresight_dev_type type,
723 union coresight_dev_subtype subtype);
724struct coresight_device *
725coresight_find_output_type(struct coresight_platform_data *pdata,
726 enum coresight_dev_type type,
727 union coresight_dev_subtype subtype);
728
729int coresight_init_driver(const char *drv, struct amba_driver *amba_drv,
730 struct platform_driver *pdev_drv, struct module *owner);
731
732void coresight_remove_driver(struct amba_driver *amba_drv,
733 struct platform_driver *pdev_drv);
734int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode,
735 struct coresight_device *sink);
736#endif /* _LINUX_COREISGHT_H */
737

source code of linux/include/linux/coresight.h

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