SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

A garden of small programming language implementations 🪴

A pedagogic implementation of abstract bidirectional elaboration for dependent type theory.

A Teeny Type Theory

implementation deriving for idris2

prototype implementation of a dependently-typed language with an extendable constraints and accompanying materials

An automated model car that tracks and follows objects. Built with RaspberryPi and Arduino, controlled by an iPhone.

Scrappy implementations of programming language ideas

Agda formalisation of an elaborator for a simply typed language

Dieses Repository enthält die Analysen sowie das Dashboard. Es umfasst R‑Skripte zur Datenaufbereitung und statistischen Auswertung (u. a. Beta‑Regressionen) sowie eine statische und interaktive Dashboard‑Seite zur Visualisierung zentraler KPIs. Das README.md dient der Navigation und enthält relevante Metadaten.

Designing SPI Slave with Single Port RAM using questasim and vivado.

VHDL 87/93/2002/2008 simulator