The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Smart Automation Controller for Precision Agriculture

Hardware-accelerated 3×3 median filter SoC on Altera DE2 (Cyclone II) using Nios II CPU, Avalon-MM bus, and a pipelined sorting-network IP core — implemented in Verilog with Quartus II 13.0 SP1.

Uart memory mapped with Avalon-MM interface

FPGA/SoPC review lab repository covering Quartus, Platform Designer/Qsys, Verilog custom IP, Avalon-MM and Nios II C.

An end-to-end Signal Processing & Telemetry SoC for Intel Cyclone V. Features a custom VHDL 4-tap FIR filter pipeline, Nios II soft processor integration via Avalon-MM, and hardware-mapped SPI, I2C, and JTAG UART communication fabrics. Modeled in MATLAB and verified using ModelSim analog waveforms.