A final year undergraduate major project. (Dec 2019 - Mar 2020)

• Developed 18 executable instructions and 7 components of a processor using Verilog HDL on Xilinix ISE.
• All modules were verified and tested (individually+combined) using testbenches and test programs on ISim simulator.

Documents
The below documents constains information on ISA table, individual blocks and its testing and final 5 test programs to test all functionalities of the processor.

• Final submitted report
• Final presentation

Design Files

1. Top module
2. Arithmetic and Logic Unit
3. Decoder
4. Memory
5. Register
6. Flag Register
7. General Purpose Register
8. Instruction Register
9. Program Counter

TestBench Files

1. Top module
2. Arithmetic and Logic Unit
3. Memory
4. Register
5. General Purpose Register
6. Instruction Register
7. Program Counter