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1. Pipelined-RV32-SoC Pipelined-RV32-SoC Public

   Forked from akira2963753/Pipelined-RV32-SoC

   32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss data with BRAM using the AXI bus.

   Verilog 1

2. RV32I RV32I Public

   Forked from CharanK-glitch/RV32I

   Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applicat…

   Verilog 1

3. riscv_cpu riscv_cpu Public

   Forked from Azalea8/riscv_cpu

   riscv指令集，单周期以及五级流水线CPU

   Verilog 1

4. RFSoC-Book RFSoC-Book Public

   Forked from dnorthcote/RFSoC-Book

   Companion Jupyter Notebooks for the RFSoC-Book.

   Jupyter Notebook 1

5. simple_riscv_soft_core simple_riscv_soft_core Public

   Forked from Rzfly/simple_riscv_soft_core

   This is a simple Risc-v core for software simulation on FPGA.

   Verilog 1

6. VexRiscv VexRiscv Public

   Forked from SpinalHDL/VexRiscv

   A FPGA friendly 32 bit RISC-V CPU implementation

   Assembly 1