8-bit computer in Verilog
This project contains:
- a 8-bit CPU with a basic instruction set
- 256 bytes of RAM
Build an exemple:
./asm/asm.py tests/multiplication_test.asm > memory.list
Run the computer:
| Instruction |
Description |
lda |
Alias for mov A M D |
sta |
Alias for mov M A D |
ldi r D |
Load D into r register |
mov r M D |
Copy the data at memory address D into register r |
mov r2 r1 |
Copy register r1 into r2 |
mov M r D |
Copy the data from register r into memory in address D |
Legend:
- D is a byte of data. It can be a memory address or directly the data depending on the instruction.
- r is a register.
- M means "memory", it's used to tell to the
mov instruction the source/destination of the copy.
| Instruction |
Description |
add |
Perform A = A + B (A, B are registers) |
adc |
Perform A = A + B + carry (A, B are registers) |
sub |
Perform A = A - B (A, B are registers) |
inc |
Perform A = A + 1 (A is a register) |
dec |
Perform A = A - 1 (A is a register) |
cmp |
Perform A - B without updating A, just update flags |
| Instruction |
Description |
and |
Perform A = A AND B (A, B are registers) |
or |
Perform A = A OR B (A, B are registers) |
xor |
Perform A = A XOR B (A, B are registers) |
| Instruction |
Description |
jmp D |
Jump to D |
jz D |
Jump to D if flag zero is set |
jnz D |
Jump to D if flag zero is not set |
je D |
Jump to D if register A equals register B after cmp (alias jz) |
jne D |
Jump to D if register A doesn't equal register B after cmp (alias jnz) |
jc D |
Jump to D if carry flag is set |
jnc D |
Jump to D if carry flag is not set |
call D |
Call sub-routine D |
ret |
Return to the parent routine |
| Instruction |
Description |
nop |
Do nothing |
hlt |
Halt the CPU |
| Instruction |
Description |
in D |
Put the content of the data bus in the A register and set D on address bus |
out D |
Put the content of accumulator on the data bus and set D on address bus |
| Instruction |
Description |
push r |
Push the content of register r on the stack |
pop r |
Pop the content from the stack and put it into register r |
T1 and T2 are always FETCH_PC and FETCH_INST.
List of instruction associated with states:
| Instruction |
T3 |
T4 |
T5 |
T6 |
T7 |
NOP |
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ALU |
ALU_EXEC |
ALU_STORE |
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CMP |
ALU_EXEC |
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OUT |
FETCH_PC |
SET_ADDR |
OUT |
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IN |
FETCH_PC |
SET_ADDR |
IN |
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HLT |
HALT |
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JMP |
FETCH_PC |
JUMP |
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LDI |
FETCH_PC |
SET_REG |
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MOV |
MOV_FETCH |
MOV_LOAD |
MOV_STORE |
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CALL |
FETCH_PC |
SET_REG |
FETCH_SP |
PC_STORE |
TMP_JUMP |
RET |
INC_SP |
FETCH_SP |
RET |
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PUSH |
FETCH_SP |
REG_STORE |
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POP |
INC_SP |
FETCH_SP |
SET_REG |
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States versus signals enabled:
| States |
II |
CI |
CO |
RFI |
RFO |
EO |
EE |
MI |
RO |
RI |
HALT |
J |
SO |
SD |
SI |
MEM/IO |
ALU_EXEC |
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X |
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ALU_STORE |
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X |
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X |
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FETCH_INST |
X |
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X |
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FETCH_PC |
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X |
X |
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X |
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FETCH_SP |
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X |
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X |
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HALT |
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X |
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INC_SP |
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X |
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IN |
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X |
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X |
JUMP |
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* |
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* |
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* |
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MOV_FETCH |
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* |
* |
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* |
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MOV_LOAD |
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* |
* |
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* |
* |
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MOV_STORE |
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* |
* |
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* |
* |
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OUT |
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X |
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X |
PC_STORE |
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X |
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X |
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REG_STORE |
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X |
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X |
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X |
X |
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RET |
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X |
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X |
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X |
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SET_ADDR |
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X |
X |
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SET_REG |
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X |
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X |
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TMP_JUMP |
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X |
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X |
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X |
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X |
X |
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CLK:
+-+ +-+ +-+ +-+ +-+ +-+ +
| | | | | | | | | | | | |
| | | | | | | | | | | | |
+ +-+ +-+ +-+ +-+ +-+ +-+
CYCLE_CLK:
+---+ +---+
| | | |
| | | |
+ +---+---+ +---+---+
MEM_CLK:
+---+ +---+
| | | |
| | | |
+---+ +---+---+ +---+
INTERNAL_CLK:
+---+ +---+
| | | |
| | | |
+---+---+ +---+---+ +