Parameterised dual-clock-domain asynchronous FIFO verified under UVM 1.2. Built for an IC verification engineer portfolio and interview use case.

参数化双时钟域异步 FIFO 在 UVM 1.2 下的验证平台，结构紧凑、面向数字 IC 验证求职与面试演示场景。

• Environment / 环境：EDA Playground, Questa Sim-64 2025.2, UVM 1.2.
• Configuration / 配置：DATA_WIDTH=8, FIFO_DEPTH=16, WR_CLK_PERIOD=10ns, RD_CLK_PERIOD=13ns.
• All runs end with UVM_ERROR=0 and UVM_FATAL=0 / 所有用例无 error/fatal.
• Pass criteria live in docs/REGRESSION_RESULTS.md.

async_fifo_uvm/
|-- rtl/
|   |-- async_fifo.sv        # Gray-coded parameterised FIFO / Gray 码参数化 FIFO
|   `-- sync_2ff.sv          # Generic 2-FF synchronizer / 两级同步器
|-- tb/
|   |-- top_tb.sv            # Clocks, reset controller, run_test / 时钟、复位、入口
|   |-- include/             # Interface, transaction, env, scoreboard, coverage
|   |-- sequences/           # basic / boundary / cdc / reset / virt
|   `-- tests/               # one UVM test per scenario / 每场景一测试
|-- edaplay/
|   `-- testbench_onefile.sv # Verified one-file EDA Playground source / 单文件
|-- docs/
|   |-- REGRESSION_RESULTS.md
|   |-- SOURCE_MAP.md
|   `-- assets/
|       |-- ARCHITECTURE.md
|       `-- WAVEFORM_GUIDE.md
|-- Makefile
|-- run.bat
|-- README.md
|-- .gitattributes
`-- .gitignore

1. Select Questa Sim-64 2025.2 and UVM 1.2 / 选择 Questa 与 UVM 1.2。
2. Leave the website design.sv editor empty / design.sv 留空。
3. Paste all of edaplay/testbench_onefile.sv into testbench.sv / 将单文件全部粘贴至 testbench.sv。
4. Leave Compile Options empty / Compile Options 留空。
5. Put one test argument in Run Options / 在 Run Options 选择测试：

+UVM_TESTNAME=fifo_basic_test
+UVM_TESTNAME=fifo_boundary_test
+UVM_TESTNAME=fifo_cdc_test
+UVM_TESTNAME=fifo_reset_test

If no argument is supplied, the top defaults to fifo_basic_test. A successful run must show non-zero traffic, mismatches=0, [SB] PASSED, UVM_ERROR=0, and UVM_FATAL=0 / 没有 +UVM_TESTNAME 时默认运行 fifo_basic_test，判据同上。

.\run.bat                        # default fifo_basic_test / 默认基础测试
.\run.bat fifo_boundary_test     # boundary guard stress / 边界保护压测
.\run.bat fifo_cdc_test          # cross-domain corners / 跨时钟域压测
.\run.bat fifo_reset_test        # EventPool async reset / EventPool 异步复位

make and make TEST=fifo_boundary_test are equivalent / 等效 Makefile 入口。

tb/include/fifo_types.svh is the single compile-time configuration point.

Example Questa override / Questa 编译期覆写：

+define+DATA_WIDTH=16 +define+FIFO_DEPTH=32

The default 8×16 configuration has been fully regressed. Other combinations are source-supported but should be re-verified before being claimed in the resume / 默认配置已完成回归，其他组合需要额外回归后再写入简历。

• fifo_seq_item carries direction, payload, and inter-transaction delay.

• fifo_driver never reads wr_full / rd_empty; it pushes every request so the DUT guard logic can be probed.

• fifo_monitor samples per clock domain and labels every transaction as accepted or guarded.

• fifo_scoreboard maintains a reference queue, compares registered read data after the NBA region, and clears the queue via EventPool on reset.

• fifo_coverage samples cross product of data, count and guard flag.

• fifo_agent, fifo_env, and fifo_virtual_sequencer form the UVM hierarchy.

• fifo_seq_item 携带方向、数据和事务间延迟。

• fifo_driver 不读取 wr_full/rd_empty，所有请求都下发，便于测试 DUT 边界保护逻辑。

• fifo_monitor 按时钟域采样并打上 guard_hit 标签。

• fifo_scoreboard 维护参考队列，在 NBA 区后比较读数据，收到复位事件后 非阻塞清空队列。

• fifo_coverage 收集数据、计数、保护三者的功能覆盖率。

• fifo_agent / fifo_env / fifo_virtual_sequencer 组成标准 UVM 层次。

1. fifo_reset_seq triggers global EVT_RESET_REQUEST.

2. top_tb is the sole owner of reset pins and asserts both resets.

3. Reset deassertion happens on the negedge to avoid the sampling race.

4. The controller waits for both clock domains to recover, then triggers EVT_RESET_DONE once.

5. The scoreboard's independent event-wait task clears the expected queue without blocking the analysis port.

6. fifo_reset_seq 触发全局 EVT_RESET_REQUEST。

7. top_tb 独占复位引脚并下拉两侧复位。

8. 复位在负边沿释放，避免采样竞争。

9. 控制器等待两个时钟域恢复后只触发一次 EVT_RESET_DONE。

10. Scoreboard 独立任务非阻塞清空期望队列，不影响分析端口。

Both top-level variants dump top_tb.vcd to the simulator working directory. The conceptual trace for the reset recovery window is in docs/assets/WAVEFORM_GUIDE.md.

No third-party RTL is bundled. Add an explicit repository license before publishing or redistributing the project.

本仓库未附带任何第三方 RTL。在公开发布或分发之前，请补充仓库的明确许可声明。