Level RISC-V

Open-source, 5-stage in-order, RV32IMC RISC-V processor core.
Built for simulation, verification, and SoC experiments with a comprehensive toolchain.

Normalized bars use 1.00 as a fixed visual baseline for fast scanning. Detailed methodology, raw counters, and reproduction commands stay in Benchmark scores.

• It is not a minimal core: the front-end includes RV32C handling, an align buffer, branch prediction, and cache-backed fetch.
• It is built for verification work: Spike comparison, riscv-tests, riscv-arch-test, Imperas flows, and optional riscv-dv / formal hooks are already integrated.
• It is parameterized for experiments: prefetch mode, cache hierarchy, multiplier/divider implementation, and simulation profiles are all configurable.
• It is easy to inspect: commit traces, Konata exports, dashboards, and memory-size reports are first-class workflows.

Click the badge above to open the live interactive architecture diagram in your browser (via htmlpreview.github.io). Tabs: Pipeline · Cache & MMU · SoC & Peripherals · Branch Predictor · Memory Map

SoC / pipeline / memory / Wishbone / benchmarks: styled one-pager in docs/level_riscv_core_diagram.html (open locally or use the badge via htmlpreview.github.io). GitHub’s README renderer does not apply custom CSS, so this replaces the old static mcu_diagram.png slide.

After runs under results/logs/<sim>/, make dashboard builds a browsable HTML report for:

• ISA, benchmark, and regression-family grouping
• pass/fail summaries plus Spike diff drill-down
• quick navigation from failing runs into logs and artifacts

Illustrative preview:

_{Stylized preview — open the generated index.html after make dashboard for live data.}

Tools this repo integrates with day to day. Click a badge to open the upstream project where applicable.

	Tool	Role in Level
	RISC-V ISA	Instruction set & compliance references
	Verilator	Primary fast RTL simulation (C++ model)
	Python 3	Test runner, ELF/MEM helpers, dashboards, config tooling
	GNU Make	Single root makefile orchestrates sim, tests, synth helpers
	RISC-V GCC riscv32-unknown-elf-	Compiles ISA / benchmark / custom C tests
	Spike	Golden reference for commit-trace comparison
	Yosys	Lint / synthesis / structural checks (make yosys, make lint)
	ModelSim / Questa	Optional event-driven sim + GUI waves
	GTKWave / Surfer	View FST/VCD from Verilator or ModelSim
	Konata	Pipeline trace viewer (Konata logger in RTL)
	riscv-dv	Optional random ISA stimulus (make riscv_dv_*)
	riscv-formal	Optional bounded / formal checks (make formal*)

Prerequisites: Verilator 5+, RISC-V GCC (riscv32-unknown-elf-*), Python 3.8+, GNU Make. Optional: Spike, Yosys, ModelSim, GTKWave/Surfer.

git clone https://github.com/kerimturak/level-v.git
cd level-v

# Build the Verilator model
make verilate

# One-shot: fetch + build + import Berkeley ISA tests (needs subrepo / toolchain)
make isa_auto

# Run one test (RTL + Spike compare by default)
make run T=rv32ui-p-add

# Run the ISA regression suite
make isa

# Help
make help

Useful shortcuts: make t T=<isa-test>, make run T=<name>, make quick_test T=<name> (RTL only). See make help_tests and make help_sim.

├── rtl/                 # Core, MMU/cache, peripherals, wrappers, pkg, flist.f
├── sim/                 # C++ TB, test lists, custom C tests
├── env/                 # Per-test link scripts & runtime for each suite
├── script/              # Python tools, shell helpers, JSON/.conf profiles
├── subrepo/             # riscv-tests, arch-test, Imperas, CoreMark, Embench, BEEBS, …
├── docs/                # Deep-dive markdown + MkDocs site source
├── makefile             # Single entry point for sim, tests, synth helpers
└── results/             # Logs, waves, dashboards (generated)

Configuration: simulator JSON under script/config/verilator.json & modelsim.json; simulation profile keys in script/config/tests/*.conf (merged with default.conf). Override with TEST_CONFIG=..., MAX_CYCLES=..., etc.

For on-chip RAM sizing and env/*/link.ld LENGTH, the relevant figure is the dec column from riscv32-unknown-elf-size (text + data + bss), which includes heap/stack reservations when the linker script places them in the image (e.g. CoreMark .heap / .stack NOLOAD regions).

Refresh numbers any time after (re)building tests:

make levelv_memory_report

These are upper bounds per suite — individual tests can be smaller. riscv-arch-test images are aimed at simulation / compliance flows and can be hundreds of KiB; they are not representative of small FPGA BRAM.

Sorted by name (one row per .elf under build/tests/embench/elf/ after make embench_build):

UART / .mem note: .mem file line count is driven by the binary image (+ optional padding, e.g. COREMARK_MEM_PAD_BYTES in the makefile). Smaller linker images yield smaller .mem files for FPGA programming.

Site: kerimturak.github.io/level-v — architecture, tools, sim guides, cache tuning, exception priority, Wishbone, and more.

Local: mkdocs serve if you use MkDocs, or browse docs/ directly. Highlights:

OpenLane flow assets live under asic/openlane/. Example GDS snapshot:

Results below are from Verilator RTL simulation at CPU_CLK_HZ=25_000_000. If you want an apples-to-apples comparison against another core, keep the workload, ISA/ABI, clock, linker constraints, and compiler flags identical. Both runs use the repo's riscv32-unknown-elf-gcc toolchain; the CoreMark UART banner reported GCC15.1.0.

1. Fork and branch from main.
2. Match RTL style: one module per file, level_param parameters, consistent *_i / *_o suffixes.
3. Run make lint before opening a PR.

GPLv3 — see LICENSE.

Kerim Turak

Level — a documented RV32IMC core for simulation, verification, and SoC experiments.