block Example(in a, in b, out c) logic {
    ret tempassign c [always 7:0] <= a + b;
}
// NOTE tempassign assign a value to a variable for only that block. The [always MSB:LSB] identifier can be assigned to either the result, or expression.

piece ExampleBus {
    in addr, in data, out ready
}
pieced block Example(ExampleBus <= bus){}

block top(in x, in y, out z) logic {
    n1 passparams example(x,y,z);
    ret z <= n1;
}

known macro1 <= clk, rst;
// pass into block
block macroeater(in clk, in rst) {} 

testbench random target(RandomBlock){
    getvars(signal1, signal2, !signal3, clk, rst);
// "!" before a var (in getvars) indicates it should never be included, if, for example, "*" is passed as an argument (which means "all")
    when(BEGIN){
        put signal1 <= 1;
        /10 expect(signal2 == 1);
        pulse len(clk), gap(rst);
        /50 watchfor req <= ack & /100 out(status);
       writefile(mode vcd, file output.vcd); 
    }
}

testgroup ExampleGroup {
    do tb_random;
    same {
        tb1
        tb2
    } // "same" = synchronous running;
}

aff posedge(clk) or negedge(rst) {}

// simple.neoh

block Example(in a, in b, out c) logic {
    ret c <= a + b;
}

testbench Verification target(Example) {
    getvars(a, b, c);
    when(BEGIN) {
        put a <= 1;
        put b <= 2;
        /100 out("Hello Neo!");
    }
}