This repository owns a binary search tree algorithm implemented as a RTL IP for FPGA and ASIC. It is designed with SystemVerilog.

• the functional specification
• the info document provides basic information about this type of algorithm
• the interface document provides information about the interface of the IP and how to use it

BSTer simulation relies for simulation on:

• Icarus Verilog
• SVUT

This IP core is licensed under MIT license. It grants nearly all rights to use, modify and distribute these sources. However, consider to contribute and provide updates to this core if you add feature and fix, would be greatly appreciated :)