Holistic Review

Motivation: The motivation is real and well-evidenced. On SVE, boolean masks are naturally predicates, but the JIT currently materializes predicate results into vectors (mov z, p/z, #1) and re-compares them to zero before doing logical ops, then compares back. Recovering the predicate form lets the JIT emit and/bic/orr/eor/sel/zip1 directly on predicate registers and reuse the first predicate as the governing predicate, removing redundant ptrue/mov sequences. The PR's own SPMI diffs show real code-size and allocation wins.

Approach: The approach is reasonable and consistent with existing patterns: recognize mask-shaped operands (ConvertMaskToVector, real masks, vector zero, and constant 0/1 vectors) during gtFoldExprHWIntrinsic and in arm64 lowering, and fold to the _Predicates intrinsic variants. Importing Sve.BitwiseClear as AND(NOT(...)) and recovering bic in lowering mirrors the established AdvSimd handling. The codegen using op1Reg as the governing predicate matches the documented and Pd, Pn/z, Pn, Pm semantics.

Summary: ⚠️ Needs Changes. The direction and most of the implementation look sound, but TryLowerSvePredicateBitwiseClear ends with an unconditional return true; in its fall-through path. Since the helper now runs for every arm64 vector GT_AND, a true result when no predicate pattern matched causes the caller to break and skip the pre-existing AdvSimd ~op1 & op2 → BitwiseClear (AndNot) folding for ordinary vector ANDs. This is a functional regression outside the intended SVE-predicate scope and is not covered by the added SVE-only tests. See the inline comment for details.

Detailed Findings

❌ Correctness — Unconditional return true; disables AdvSimd AndNot folding

Flagged inline at src/coreclr/jit/lowerarmarch.cpp fall-through return. The final return true; should be return false; so that non-predicate vector ANDs fall through to the existing NI_AdvSimd_BitwiseClear/AndNot recognition in LowerHWIntrinsic. As written, that established optimization is bypassed for all arm64 vector GT_AND whose operands are not mask-shaped.

⚠️ Test coverage — No coverage for the non-predicate AndNot path

The added tests in PredicateInstructions.cs exercise only the new SVE-predicate folds (all inputs mask-shaped). None exercise an ordinary vector ~a & b / Vector*.AndNot on arm64, which is exactly the path broken by the finding above. A regression test covering that AdvSimd AndNot lowering would prevent this class of regression.

✅ Codegen and fold logic — Predicate variants look correct

The NI_Sve_And_Predicates/NI_Sve_BitwiseClear_Predicates codegen reusing op1Reg as the governing predicate matches the SVE semantics in the PR description, and the 0/1-vector-to-mask recognition in gtFoldExprHWIntrinsic is guarded to arm64 + masked HW intrinsics and rejects non-0/1 constants. TryLowerSveConvertVectorToMask correctly only elides the conversion when the source is already a mask.

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