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Commits on May 22, 2020

• Don't ever skip off duty, no matter if late or infinitely short.

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• Small refactoring, remove code path that is never taken even at 3x25kHz/1023 PWM.

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Commits on May 21, 2020

• New PWM overshoot mitigation code keeps frequency. Averages duty between consecutive periods.

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Commits on May 20, 2020

• Overshoot mitigation w/o PWM frequency change.

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Commits on May 17, 2020

• SDK boost to 160MHz may last across multiple ISR invocations, therefore adjust target ccy instead of ccount.

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Commits on May 16, 2020

• Reduce memory use.

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Commits on May 14, 2020

• Guards are in place, so xor rather than and bitwise not.

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Commits on May 12, 2020

• Save a few bytes code.

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• Recalibrate after latest changes.

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• Expired pins must not be checked for next event.

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Commits on May 11, 2020

• Event timestamps are all recorded for compile-time CPU frequency, the timer ticks conversion

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Commits on May 10, 2020

• Mitigation logic for ESP8266 SDK boosting to 160MHz during some WiFi ops.

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• Increase resolution by keeping reference time moving forward earlier.

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Commits on May 9, 2020

• Fixing overshoot mitigation, 3x 880Hz, 256 states now.

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• Much simplified overshoot mitigation code.

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• Revert recent change that is the most likely cause of reported PWM frequency drop regression.

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Commits on May 8, 2020

• Reverting maximum IRQ period to 10ms. This sets the wave reprogramming rate to 100Hz max.

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• Dynamically map pins out from in-ISR handling based on next event timing.

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• Code simplifications.

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• Shorten progression when going off 100% duty.

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• Memory fences checked and joining events into same loop iteration that are close to one another.

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• Simple register writes.

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• Off-by-one in 100% duty overshoot correction.

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• Recalibrated delta irq ccys.

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• Seems that removing the redudant resetting of edge interrupt mode shaves 0.5us off rearm latency.

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• 80MHz/160MHz specific code can be compile-time selected in general, only NMI is affected by

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• Let duty cycle overshoot correction depend on relative impact compareed to both period and duty.

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• Corrected use of Timer1 registers and add rationale to Timer1 use in comment.

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• CPU clock to Timer1 ccy correction must be dynamic even when BSP is compiled for fixed CPU clock.

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• Recalibrated DELTAIRQ and IRQLATENCY. Tested @ 3x 40kHz PWM + 440Hz Tone

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• Persist next event cycle across ISR invocations, like initPin was before.

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• Move startPin etc. into common static struct

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• Improved duty cycle overshoot mitigation.

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• Improved idle cycle overshoot mitigation.

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• Finally get rid of volatile and use atomic thread fence memory barriers, great for ISR performance.

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