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Commit b1e3140

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1 parent 9338442 commit b1e3140
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‎cores/esp8266/core_esp8266_waveform.cpp

Copy file name to clipboardExpand all lines: cores/esp8266/core_esp8266_waveform.cpp
+15-12Lines changed: 15 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,8 @@ int startWaveformClockCycles(uint8_t pin, uint32_t highCcys, uint32_t lowCcys,
170170
wave.autoPwm = autoPwm;
171171

172172
std::atomic_thread_fence(std::memory_order_acquire);
173-
if (!(waveform.enabled & (1UL << pin))) {
173+
const uint32_t pinBit = 1UL << pin;
174+
if (!(waveform.enabled & pinBit)) {
174175
// wave.nextPeriodCcy and wave.endDutyCcy are initialized by the ISR
175176
wave.nextPeriodCcy = phaseOffsetCcys;
176177
wave.expiryCcy = runTimeCcys; // in WaveformMode::INIT, temporarily hold relative cycle count
@@ -182,7 +183,7 @@ int startWaveformClockCycles(uint8_t pin, uint32_t highCcys, uint32_t lowCcys,
182183
GP16O = 0;
183184
}
184185
else {
185-
GPOC = 1UL << pin;
186+
GPOC = pinBit;
186187
}
187188
}
188189
std::atomic_thread_fence(std::memory_order_release);
@@ -223,7 +224,8 @@ int ICACHE_RAM_ATTR stopWaveform(uint8_t pin) {
223224
// If user sends in a pin >16 but <32, this will always point to a 0 bit
224225
// If they send >=32, then the shift will result in 0 and it will also return false
225226
std::atomic_thread_fence(std::memory_order_acquire);
226-
if (waveform.enabled & (1UL << pin)) {
227+
const uint32_t pinBit = 1UL << pin;
228+
if (waveform.enabled & pinBit) {
227229
waveform.toDisable = pin;
228230
std::atomic_thread_fence(std::memory_order_release);
229231
// Must not interfere if Timer is due shortly
@@ -335,8 +337,9 @@ static ICACHE_RAM_ATTR void timer1Interrupt() {
335337
} while (static_cast<int32_t>(isrNextEventCcy - now) > 0);
336338
isrNextEventCcy = isrTimeoutCcy;
337339
do {
340+
const uint32_t pinBit = 1UL << pin;
338341
// If it's not on, ignore
339-
if (!(busyPins & (1UL << pin)))
342+
if (!(busyPins & pinBit))
340343
continue;
341344

342345
Waveform& wave = waveform.pins[pin];
@@ -345,13 +348,13 @@ static ICACHE_RAM_ATTR void timer1Interrupt() {
345348
if (WaveformMode::EXPIRES == wave.mode && wave.nextEventCcy == wave.expiryCcy &&
346349
static_cast<int32_t>(overshootCcys) >= 0) {
347350
// Disable any waveforms that are done
348-
waveform.enabled &= ~(1UL << pin);
349-
busyPins &= ~(1UL << pin);
351+
waveform.enabled &= ~pinBit;
352+
busyPins &= ~pinBit;
350353
}
351354
else {
352355
if (static_cast<int32_t>(overshootCcys) >= 0) {
353356
uint32_t nextEdgeCcy;
354-
if (waveform.states & (1UL << pin)) {
357+
if (waveform.states & pinBit) {
355358
// active configuration and forward are 100% duty
356359
if (wave.periodCcys == wave.dutyCcys) {
357360
wave.nextPeriodCcy += wave.periodCcys;
@@ -368,12 +371,12 @@ static ICACHE_RAM_ATTR void timer1Interrupt() {
368371
}
369372
else {
370373
nextEdgeCcy = wave.nextPeriodCcy;
371-
waveform.states &= ~(1UL << pin);
374+
waveform.states &= ~pinBit;
372375
if (16 == pin) {
373376
GP16O = 0;
374377
}
375378
else {
376-
GPOC = 1UL << pin;
379+
GPOC = pinBit;
377380
}
378381
}
379382
}
@@ -396,12 +399,12 @@ static ICACHE_RAM_ATTR void timer1Interrupt() {
396399
if (WaveformMode::EXPIRES == wave.mode)
397400
wave.expiryCcy += adj * wave.periodCcys;
398401
}
399-
waveform.states |= 1UL << pin;
402+
waveform.states |= pinBit;
400403
if (16 == pin) {
401404
GP16O = 1;
402405
}
403406
else {
404-
GPOS = 1UL << pin;
407+
GPOS = pinBit;
405408
}
406409
}
407410
nextEdgeCcy = wave.endDutyCcy;
@@ -413,7 +416,7 @@ static ICACHE_RAM_ATTR void timer1Interrupt() {
413416
}
414417

415418
if (static_cast<int32_t>(wave.nextEventCcy - isrTimeoutCcy) >= 0) {
416-
busyPins &= ~(1UL << pin);
419+
busyPins &= ~pinBit;
417420
if (static_cast<int32_t>(waveform.nextEventCcy - wave.nextEventCcy) > 0) {
418421
waveform.nextEventCcy = wave.nextEventCcy;
419422
waveform.nextPin = pin;

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