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Verilog parser doesn't handle legal identifiers correctly

Status: Open.

#38 In circuitgraph/circuitgraph;

· bsferrazza opened on Dec 27, 2025

Error while creating a circuit through file

Status: Open.

#36 In circuitgraph/circuitgraph;

· jenila19 opened on Oct 14, 2023

Nodes from blackboxes are not presented correctly.

Status: Open.

#30 In circuitgraph/circuitgraph;

· zyk101177 opened on Jun 14, 2021

Add ability to parse busses

enhancementNew feature or requestNew feature or request

Status: Open.

#29 In circuitgraph/circuitgraph;

· rbnprdy opened on May 25, 2021

Clean up netlists

Status: Open.

#28 In circuitgraph/circuitgraph;

· rbnprdy opened on May 25, 2021

Add parsing for "x" valued nodes.

Status: Open.

#27 In circuitgraph/circuitgraph;

· rbnprdy opened on May 25, 2021

from_file(path="/netlists/lut_1.v", name="LUT_WINPUT1") fails on lexer

Status: Open.

#26 In circuitgraph/circuitgraph;

· roy-pstr opened on May 11, 2021

todo

Status: Open.

#25 In circuitgraph/circuitgraph;

· jpsety opened on Mar 28, 2021

Interfaces

Status: Open.

#20 In circuitgraph/circuitgraph;

· prw99r opened on Nov 10, 2020

Synthesis Coverage

Status: Open.

#19 In circuitgraph/circuitgraph;

· prw99r opened on Nov 10, 2020

speed up with caching

Status: Open.

#12 In circuitgraph/circuitgraph;

· jpsety opened on Sep 18, 2020

Add ability to parse concatenation syntax

enhancementNew feature or requestNew feature or request

Status: Open.

#2 In circuitgraph/circuitgraph;

· rbnprdy opened on Jul 30, 2020