Skip to content

Navigation Menu

Sign in
Appearance settings

Search code, repositories, users, issues, pull requests...

Provide feedback

We read every piece of feedback, and take your input very seriously.

Saved searches

Use saved searches to filter your results more quickly

Appearance settings

fix: Megatron async checkpoint CUDA memory retention#3322

Open
NolenLiang wants to merge 1 commit into
mainNVIDIA-NeMo/RL:mainfrom
nliang/fix-3244-megatron-memoryNVIDIA-NeMo/RL:nliang/fix-3244-megatron-memoryCopy head branch name to clipboard
Open

fix: Megatron async checkpoint CUDA memory retention#3322
NolenLiang wants to merge 1 commit into
mainNVIDIA-NeMo/RL:mainfrom
nliang/fix-3244-megatron-memoryNVIDIA-NeMo/RL:nliang/fix-3244-megatron-memoryCopy head branch name to clipboard

Conversation

@NolenLiang

@NolenLiang NolenLiang commented Jul 23, 2026

Copy link
Copy Markdown
Contributor

What does this PR do?

Fixes #3244 by releasing checkpoint-owned CUDA IPC state before colocated Megatron offload replaces model and optimizer storage.

With asynchronous NVRx checkpointing, the persistent checkpoint writer caches CUDA tensor handles when constant-structure caching is enabled. Finalizing the active save removes the request, but it does not release the writer-side cache. After offload replaces the model or optimizer storage, those handles keep the old GPU allocations alive. In the reported workload, this retained approximately 19.2 GiB per rank and caused the subsequent vLLM wakeup to fail with CUDA OOM.

This change:

  • Finalizes pending checkpoint writes before both before-refit and after-refit offload paths replace CUDA storage.
  • Limits persistent-writer teardown to the affected configuration: colocated generation, asynchronous NVRx, persistent checkpoint worker, constant-structure caching, and no CPU shared-memory checkpoint staging.
  • Terminates the completed writer, clears FileSystemWriterAsync tensor caches, runs Python garbage collection, and releases CUDA IPC and allocator caches.
  • Allows NVRx to recreate its persistent writer lazily for the next checkpoint.
  • Adds lifecycle tests for both offload paths and for active/inactive cache cleanup behavior.

User impact

Asynchronous checkpointing remains enabled. The additional synchronization and cleanup only occur at storage-replacement boundaries for the affected colocated configuration. Other checkpoint strategies and non-colocated workloads retain their existing behavior.

Validation

  • Targeted MCore tests: 4 passed, 15 deselected.
  • Pre-commit checks: all applicable hooks passed, including Ruff, Ruff format, pyrefly, and recipe checks.
  • Full VLM GRPO acceptance run: 4 nodes × 8 H100 GPUs × 20 training steps.
    • Step 10 and Step 20 asynchronous checkpoints both completed and finalized.
    • Post-checkpoint Megatron allocation decreased from approximately 27.04 GiB per rank in the failing run to approximately 7.85 GiB per rank.
    • The original post-checkpoint failure point passed, and training completed all 20 steps.
    • max(train/reward) = 0.8999998569488525 (> 0.75).
    • max(validation/accuracy) = 0.8343750238418579 (> 0.8).
    • Final scheduler status: COMPLETED, exit code 0:0.

Checklist

  • Added regression coverage for the checkpoint/offload lifecycle.
  • Ran targeted unit and full functional validation.
  • No documentation update is required because this does not change a public API or configuration.

@NolenLiang
NolenLiang requested review from a team as code owners July 23, 2026 08:53
@copy-pr-bot

copy-pr-bot Bot commented Jul 23, 2026

Copy link
Copy Markdown

This pull request requires additional validation before any workflows can run on NVIDIA's runners.

Pull request vetters can view their responsibilities here.

Contributors can view more details about this message here.

@NolenLiang NolenLiang changed the title Fix Megatron async checkpoint CUDA memory retention fix: Megatron async checkpoint CUDA memory retention Jul 23, 2026
Finalize NVRx saves before colocated offload and release persistent writer tensor caches and CUDA IPC mappings. This prevents stale checkpoint storage from blocking subsequent vLLM wakeups.

Add lifecycle coverage for both offload paths and conditional cache cleanup.

Signed-off-by: NolenLiang <nliang@nvidia.com>
@NolenLiang
NolenLiang force-pushed the nliang/fix-3244-megatron-memory branch from dd90df9 to 798eecd Compare July 23, 2026 09:30
@NolenLiang NolenLiang added the CI:L1 Run doctests, unit tests, and functional tests label Jul 23, 2026
@NolenLiang

Copy link
Copy Markdown
Contributor Author

/ok to test 798eecd

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

CI:L1 Run doctests, unit tests, and functional tests

Projects

None yet

Development

Successfully merging this pull request may close these issues.

vlm_grpo-qwen3-omni-30ba3b-audiomcq-4n8g-megatron.v1 fail in main branch

1 participant

Morty Proxy This is a proxified and sanitized view of the page, visit original site.