fix: Megatron async checkpoint CUDA memory retention#3322
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Finalize NVRx saves before colocated offload and release persistent writer tensor caches and CUDA IPC mappings. This prevents stale checkpoint storage from blocking subsequent vLLM wakeups. Add lifecycle coverage for both offload paths and conditional cache cleanup. Signed-off-by: NolenLiang <nliang@nvidia.com>
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What does this PR do?
Fixes #3244 by releasing checkpoint-owned CUDA IPC state before colocated Megatron offload replaces model and optimizer storage.
With asynchronous NVRx checkpointing, the persistent checkpoint writer caches CUDA tensor handles when constant-structure caching is enabled. Finalizing the active save removes the request, but it does not release the writer-side cache. After offload replaces the model or optimizer storage, those handles keep the old GPU allocations alive. In the reported workload, this retained approximately 19.2 GiB per rank and caused the subsequent vLLM wakeup to fail with CUDA OOM.
This change:
FileSystemWriterAsynctensor caches, runs Python garbage collection, and releases CUDA IPC and allocator caches.User impact
Asynchronous checkpointing remains enabled. The additional synchronization and cleanup only occur at storage-replacement boundaries for the affected colocated configuration. Other checkpoint strategies and non-colocated workloads retain their existing behavior.
Validation
4 passed, 15 deselected.max(train/reward) = 0.8999998569488525(> 0.75).max(validation/accuracy) = 0.8343750238418579(> 0.8).COMPLETED, exit code0:0.Checklist