_{⚙️ System Integration - Registers, Memory, ALU, Program Counter and Display Connected (Performing Addition [A] ← [A] + [B])}

• This project is my attempt to explore how computers work fundamentally at the gate level.
  I aim to design and build a fully functional 8-bit CPU from scratch.

• Before simulation, each module is designed conceptually using hand-drawn block diagrams and written reasoning to validate the logic flow through mental simulation and small example cases.
• The block diagram is then refined into a rough structural, gate-level representation before being implemented, debugged, and rigorously tested in digital logic simulators such as Logisim Evolution and Falstad.
• Where possible, I explore multiple design approaches to achieve the same functionality, comparing behavior, complexity, and design trade-offs before finalizing an implementation.

• Clock Module
• Registers
• Bus System
• ALU
• RAM
• Address Decode Logic
• Manually Programmable RAM
• Programmable_RAM_Stored Program Execution
• Program Counter
• Programmable ROM - Hex Display
• Programmable ROM - Decimal Display
• System Integration
• Stored Micro-Program Control

_{💾 Registers & Bus System}

• Clock
• Set-Only Latch

_{Clock Module}

Each module will have its own folder containing:

• A dedicated README.md explaining design, features, and usage
• Images of schematics, simulations, and hardware builds

• Understand computation from the ground up
• Document the full design and build process
• Share schematics, notes, and experiments for others to learn from

Download → download_repos.bat

Double-click it and pick the repo(s) you want.

Download → download_repos.sh

bash

chmod +x download_repos.sh
./download_repos.sh

Always downloads the latest version.

portmap is a lightweight CLI tool that extracts port definitions (input, output, inout) from Verilog modules and presents them in a clean table or Markdown format.

https://github.com/KARAN-D05/portmap-HDL/blob/main/utils/portmap

https://github.com/KARAN-D05/portmap-HDL/releases/tag/v1.0.0

portmap file.v
portmap file.v --md

Filetree - A repository file tree generator that prints a visual directory tree with file-type icons and a file count breakdown by extension (.v, .circ, .md, .py and more).

Utils (Portmap + Filetree)- Fetched automatically as a utils package alongside any repo download - includes portmap binaries, filetree, and source code via download_repos.bat / download_repos.sh.

• Source code, HDL, and Logisim circuit files are licensed under the MIT License.
• Documentation, diagrams, images, and PDFs are licensed under Creative Commons Attribution 4.0 (CC BY 4.0).