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cv32e40p
cv32e40p PublicForked from openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog
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core-v-verif
core-v-verif PublicForked from openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Assembly
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palace-aws-demo
palace-aws-demo PublicForked from LubomirJagos42/palace-aws-demo
Running palace AWD demo projects for EM simulations which are verified.
Python
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fpga-matrix-systolic-accelerator
fpga-matrix-systolic-accelerator PublicLow-level implementation of a systolic array-based matrix multiplication accelerator
Python
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