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Commits on Jun 28, 2021
Add LLInt fast path for less, lesseq, greater and greatereq
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Commits on Nov 4, 2020
[JSC] Add JITCage support
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Commits on Sep 24, 2020
[MIPS] Broken build after r267371
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Commits on Sep 22, 2020
Fix MIPS leai,leap when offset is nonzero
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Commits on Jul 8, 2020
Add a way to return early from detected infinite loops to aid the fuzzer
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Commits on Apr 18, 2020
Fix code origin when lowering offlineasm instructions on MIPS/ARM64E
Show description for 07e9a26authored andcommittedREGRESSION(r260246): It broke build on MIPS32
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Commits on Feb 26, 2020
[JSC][MIPS] Adding support to Checkpoints
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Commits on Jan 16, 2020
[JSC] 32-bit platforms should use a PC base register
Show description for c76d0adcommitted
Commits on Nov 20, 2019
[JSC] OSR exit to LLInt is broken on MIPS
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Commits on Nov 13, 2019
Split ArithProfile into a Unary and a Binary version
Show description for 8d957ffcommitted
Robin Morisset
Commits on Nov 9, 2019
Unreviewed, rolling out r252229.
Show description for bd54845committed
Commits on Nov 8, 2019
Split ArithProfile into a Unary and a Binary version
Show description for 9c844d6committedRobin Morisset
Commits on Nov 4, 2019
Unreviewed, rolling out r252015.
Show description for 619ba0ecommittedTruitt SavellSplit ArithProfile into a Unary and a Binary version
Show description for a68353bcommittedRobin Morisset
Commits on Nov 2, 2019
The offline assembler is wrong about which immediates are supported by and/or/xor on ARM64
Show description for 6d8a5f0committedRobin Morisset
Commits on Oct 31, 2019
Unreviewed, fix cloop builds after r251886
Show description for 2822c59committed
Commits on Oct 24, 2019
Disable pichdr generation on MIPS for return location labels
Show description for 96f9b6fauthored andcommitted
Commits on May 30, 2019
[JSC] Implement op_wide16 / op_wide32 and introduce 16bit version bytecode
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Commits on Jan 24, 2019
[JSC] Reenable baseline JIT on mips
Show description for a671d58committed
Commits on May 30, 2018
[MIPS] Fix build on MIPS32r1
Show description for 18ba67cauthored andcommitted
Commits on May 9, 2018
[MIPS] Use mfhc1 and mthc1 to fix assembler error
Show description for 4a9cdbbauthored andcommitted
Commits on May 8, 2018
[DFG][MIPS] Simplify DFG code by increasing MIPS temporary registers
Show description for b6ddc8dcommitted
Commits on Feb 18, 2018
Offlineasm/MIPS: immediates need to be within 16-bit signed values
Show description for 284486bauthored andcommitted
Commits on Feb 12, 2018
Miscellaneous refactoring of offlineasm.
Show description for a6aeff2committedMark Lam
Commits on Mar 14, 2016
[mips] Fix unaligned access in LLINT.
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Commits on Jan 31, 2016
[mips] don't save to a callee saved register too early
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Commits on Jan 19, 2016
[mips] Logical instructions allow immediates in range 0..0xffff, not 0x7fff
Show description for 9a98417authored andcommitted
Commits on Jan 18, 2016
[MIPS] LLInt: fix calculation of Global Offset Table
Show description for 66c2c96authored andcommitted
Commits on Jan 17, 2016
[mips] Fix regT2 and regT3 trampling in MacroAssembler
Show description for fda105bcommitted
Commits on Jan 7, 2016
[mips] Lower immediates of logical operations.
Show description for da7525aauthored andcommitted
Commits on Sep 3, 2015
Clean up register naming
Show description for 4ef519ccommitted
Commits on Sep 3, 2014
[MIPS] Wrong register usage in LLInt op_catch.
Show description for a607286authored andcommitted
Commits on Aug 12, 2014
Eliminate {push,pop}CalleeSaves in favor of individual pushes & pops
Show description for adae711committed
Commits on Jan 6, 2014
Add write barriers to the LLInt
Show description for d1ecb24committedMark Hahnenberg