⚠️ Design-stage — no hardware exists yet

DCENT_axe has not been fabricated, and no DCENT_axe board has ever mined a share. This repository holds open-hardware design files at the pre-fabrication stage. The mechanical contract, BOM, and common-platform schematic are locked; KiCad layout, first-article fabrication, and live bring-up are the work still ahead. Every hashrate, efficiency, cost, and certification figure in this repo is a design target, not a measurement — nothing is final until a fabricated board mines a real accepted share.

Built by the Mining Hackers at D-Central Technologies — Canada's leading Bitcoin mining technology company since 2016, based in Laval, Québec. 2,500+ miners repaired, 400+ products shipped. This is the bench we use ourselves, released so every operator can own, repair, and understand their own hardware.

For too long, Bitcoiners focused decentralization on a single layer — the network. But decentralization is many shades of many layers: compute, power, tools, and communication. Every DCENT_axe ships a LoRa mesh radio onboard — an off-grid voice for your miner with no Wi-Fi, no internet, no cloud relay. Each board is one node in a mesh that nobody can switch off.

We've been mesh-network proponents since 2012. That conviction is no longer buried in the hardware — it's central to the product, and it's 100% open source. Every DCENT_axe is a real weapon in the arsenal of any cypherpunk who believes sovereignty must be decentralized at every layer.

Send a raven.

📖 The full story — decentralize every layer, the communication layer, mesh since 2012, a weapon in the cypherpunk arsenal — is in MANIFESTO.md.

DCENT_axe is D-Central Technologies' own open-source Bitcoin micro-miner — a complete open-hardware product line, not "just another Bitaxe firmware fork." It is the home/solo counterpart to our industrial DCENT_OS firmware: a family of D-Central-branded, salvage-fed, JLCPCB-targeted, Bitaxe-class boards with a six-generation hardware roadmap — BM1397 / BM1398 / BM1366 / BM1368 / BM1370 / BM1362 — across three frozen form factors (Single, Quad, Hex). Firmware-supported mining targets today are BM1397 / BM1366 / BM1368 / BM1370; BM1398 and BM1362 remain first-article validation targets.

The product is built around one idea the rest of the DIY-miner ecosystem doesn't have:

Every DCENT_axe board carries an onboard SX1262 LoRa mesh radio and a universal accessory connector. It is a mining board with an off-grid voice baked in — telemetry, found-block beacons, and owner-authenticated control over kilometers, with no Wi-Fi, no internet, and no cloud.

This repository holds the open-hardware design files (KiCad projects, the binding mechanical/electrical/BOM contracts, and the JLCPCB fabrication toolchain). The firmware that runs on these boards is DCENT_OS for ESP devices — the ESP32-S3 member of the DCENT_OS family — and is owned in its own workstream.

⚠️ Read this first — honest status. DCENT_axe is an active open-hardware design at the pre-fabrication stage. The mechanical contract, BOM, and common-platform schematic are locked; KiCad layout, first-article fabrication, and live bring-up are the work ahead. No performance, certification, or hashrate claim is final until a fabricated board mines a real accepted share. See Honest Status & Roadmap — we tell you exactly what is confirmed vs. pending, the same way our other open-source tools do.

• Credits & prior art — standing on the shoulders of giants
• Why DCENT_axe
• The product line — three form factors × six chips
• The differentiator — LoRa mesh on every board
• The shared platform & the BAP accessory port
• Firmware — DCENT_OS for ESP devices
• Technical reference (the deep dive)
• Manufacturing & the salvage moat
• Honest status & roadmap
• Repository layout
• Build & verify (the toolchain)
• The D-Central open-source Bitcoin mining ecosystem
• Governance & contributing
• Licensing, certification & legal
• About D-Central Technologies

DCENT_axe did not invent the open-source Bitcoin micro-miner. It stands on the shoulders of the people and communities who did — and we want that stated plainly, up front:

• Bitaxe was created by Skot9000 (Skot Croshere) — the world's first fully open-source Bitcoin ASIC miner, given away under CERN-OHL. DCENT_axe is a Bitaxe-class board: it deliberately reuses the ESP32-S3 + BM13xx design language Skot pioneered so the community's knowledge carries straight over. Hardware repo: github.com/skot/bitaxe.
• Open Source Miners United (OSMU) — the community (Discord) that stewards Bitaxe, NerdAxe/NerdQAxe, NerdMiner and the wider open-mining ecosystem, and the reference point for everything in this class.
• ESP-Miner / AxeOS — the open firmware whose drivers, register maps, and web tooling first made an ESP32 talk to a Bitmain ASIC.
• Meshtastic and the wider LoRa ecosystem — the mesh foundations the DCENT_axe radio layer builds on.

Our contribution sits on top of that work: an onboard LoRa mesh radio, a universal accessory bus, a salvaged-ASIC supply chain, and the DCENT_OS-for-ESP firmware. If we've mis-credited anyone or missed a project we should acknowledge, please open an issue — getting the credit right matters more to us than the marketing.

The DIY Bitcoin-miner scene (Bitaxe, NerdAxe, NerdQAxe, the ESP-Miner/AxeOS firmware family) proved that a single hand-builder can run real SHA-256 silicon at home. DCENT_axe takes that proof and re-engineers it as a manufacturable, sovereign, salvage-fed product line — built by a company that has repaired thousands of these chips.

What DCENT_axe intends to add on top of the proven Bitaxe-class formula (all of it design-stage, none of it yet measured on hardware): salvaged, graded ASICs pulled from dead S17/T17 donors instead of new $12–50 chips; a universal mechanical contract so one heatsink and case fit every chip generation; an onboard SX1262 LoRa mesh on every board for off-grid telemetry; GPL-3.0 firmware with zero forced dev fee; and a CERN-OHL-S-2.0 design published with the real JLCPCB toolchain and LCSC part numbers so it is actually buildable.

The market differentiator in one sentence: designed to be the cheapest fully-JLCPCB-assembled Bitaxe-class board you can build except the hand-soldered salvaged ASIC — with a LoRa mesh radio and a universal accessory bus that nothing else in the category ships. (Cost target — gated on a live JLCPCB quote and first-article fabrication; see Honest Status.)

DCENT_axe is intentionally compatible-by-convergence with the ecosystem it admires — it reuses the ESP32-S3 + BM13xx silicon language pioneered by Bitaxe so the community's knowledge transfers — while adding the sovereignty layer (mesh + accessory bus + AI control) it aims to bring to the class. How it actually stacks up against a Bitaxe, NerdQAxe++, or NerdMiner can only be judged once a board is fabricated and mining — so this README makes no head-to-head performance claim until then.

The line is a family because of one binding rule (the Universal Mechanical Contract, locked 2026-06-26):

For each form factor, the board outline + mounting holes + heatsink interface + connector placement + ESP32-S3 / LoRa / BAP placement are FROZEN across every chip generation. The only things that change per chip are the ASIC swap-zone (footprint + exposed pad + via-stitch), the core-buck output voltage/inductor sizing, and an optional 0.8 V aux LDO (BM1370/BM1362 only).

That single law is what lets one heatsink and one case fit every generation, and lets a SKU re-skin to a new chip without a mechanical respin.

Lead board: DCENT_axe BM1397 (Single). BM1397 is the cheapest chip, has the deepest D-Central salvage pool (dead S17/S17 Pro/T17 donors), and the best-documented driver. A bad salvage pull scraps one ~$5 single-chip board, not a multi-chip assembly — so the single-chip board absorbs yield risk while the platform is proven. Grade every chip on asic-tester before assembly.

Why Quad rides a PC cooler: the Quad envelope matches the NerdQAxe++ so a standard Intel LGA115x CPU/gaming cooler bolts straight on — the quiet, cool, high-overclock "Bitaxe Quad we never had," built by riding the mature PC-cooling ecosystem instead of a bespoke block.

Mesh is core product DNA, not an accessory. Every SKU carries a mandatory onboard Ebyte E22-900M22S (true Semtech SX1262 + TCXO + LC match + RF switch + shield, LCSC C411293, FCC ID 2ALPH-E22900M22S) in a frozen, ground-moated board corner.

The load-bearing rule that makes "BAP and LoRa on every board" possible:

The SX1262 is on its own dedicated SPI bus — NEVER on the BAP. The BAP is a UART-only accessory service; the radio gets a private SPI bus so a UART-mode accessory can never knock the radio offline. This is the direct, non-negotiable consequence of putting both a BAP and a LoRa radio on every board.

What the mesh does (firmware dcentaxe-lora crate):

• A lightweight DCENT mesh stack — Telemetry, BlockFound, Identify, owner-authenticated Command, and Ack — reusing the BAP's $…,<TOK>,…*XX NMEA-style grammar.
• Off-grid fleet visibility: hashrate, temperature, and "I found a block" beacons across kilometers with no Wi-Fi/internet.
• Owner-gated control posture (the same security stance as the rest of the DCENT line).

⚠️ Firmware status (honest, 2026-07-12): the mesh stack is integrated into the dcentaxe binary behind a default-OFF lora Cargo feature (lora_task, MCP tools, honesty-gated dashboard panel). Public board features (including dcent-axe-bm1397) do not enable lora — stock images stay radio-dark so a non-functional "LoRa enabled" UI cannot ship. Pin map is netlist-locked 9/9 on BM1397; live RF / multi-node relay is unproven. The radio hardware is in the locked BOM; shipping mesh requires an explicit …,lora build + first-article RF bring-up.

DCENT_axe's mesh is harmonized with its sibling DCENT_Raven (a LoRa-mesh accessory for existing Bitaxes) — same silicon, opcodes, and mesh vocabulary; the only difference is wiring (Raven carries its own MCU as a BAP host; DCENT_axe puts the radio directly on the main ESP32-S3).

Every SKU forks one common platform (see COMMON_PLATFORM_SCHEMATIC_SKELETON.md):

• ESP32-S3-WROOM-1 N8R8 (C2913201) — host MCU. Non-octal PSRAM is deliberate: it keeps GPIO33–37 free for the LoRa/accessory budget. Do not swap to an octal-PSRAM variant.
• TI TPS546D24A (C507280) — a single 40 A digital PMBus core buck that serves 1→6 chips. Its output voltage is a register write, so a per-chip re-skin needs no power respin — only a value change.
• Data-only USB-C (ESP32-S3 native USB-Serial-JTAG — no PD, no bridge IC), EMC2101 fan controller, and an addressable status LED.

The BAP (J4) — the universal accessory bus, frozen on every board:

A 1×6, 2.54 mm through-hole header with an identical pinout on every SKU: +5V / GND / GPIO39 / GPIO40 / GPIO41 / GPIO42. It is firmware-muxed (AccessoryMode {None, BapTouch, W5500Lan}, mutually exclusive):

J4 is the mate for the sibling dcent-lan-bitaxe W5500 Ethernet add-on and the BAP-Touch pogo jig — which is why the pinout and width are frozen: never widen J4 (it breaks pogo and accessory compatibility).

DCENT_axe boards run DCENT_OS for ESP devices, the ESP32-S3 member of the DCENT_OS family — a clean-room Rust rewrite (ESP-IDF v5.3+, GPL-3.0), not a fork of ESP-Miner (protocol reference only).

• Built-in MCP (Model Context Protocol) server (one of the first mining firmwares to embed one) → with the firmware's MCP server, every board runs as an AI-controllable miner and a smart space heater.
• 9 Rust workspace crates: dcentaxe (binary) + -asic / -hal / -core / -bap / -lora / -mining / -stratum / -stratum-v2.
• Drives BM1397 (Max) / BM1366 (Ultra) / BM1368 (Supra) / BM1370 (Gamma), with Stratum V1/V2.
• Shares one DCENT Design Language with the industrial DCENT_OS firmware — convergence by design, never shared code.

The firmware is owned separately from these board designs: board changes don't touch the firmware crate, and firmware changes don't touch KiCad — unless a task explicitly crosses that boundary. For firmware work, see the DCENT_OS for ESP project.

This is the part we promised would be a holy grail. Everything below is the real engineering contract the KiCad work obeys, with live LCSC part numbers and explicit confidence tags. Full source documents are linked.

The swap-zone is sized to 8 × 8 mm so the largest die in the family drops in; all generations share the exposed-pad centroid so one heatsink lands identically regardless of chip.

KF1950 is the first non-Bitmain SKU — MicroBT / WhatsMiner K-series silicon (chip ID ~0x1950, Samsung 8 nm, 6 Mbaud UART), bootstrapped from the open-source BitshokaNini V1.1. It is a firmware research target: DCENT_OS-for-ESP has only Bitmain BM13xx drivers. D-Central already holds the KF1950 protocol RE and an (untested) industrial driver, so the remaining gap is the ESP32 port (at 6 Mbaud) + a known zero-nonce blocker — not RE from scratch. See dcent-axe-KF1950/.

Per-chip swap-zone rules: EP centroid fixed at the heatsink-pattern centre · windowed EP paste ~50–70% (never 100% flood) · tented/epoxy-filled via-in-pad stitch · hot-air keep-out ring protecting the ESP32-S3 + LoRa modules · ASIC marked DNP / excluded from the JLCPCB CPL on every SKU. Full contract: UNIVERSAL_MECHANICAL_CONTRACT.md §1.

DCENT_axe is cheapest-fully-JLCPCB-assembled except the ASIC — which D-Central hand-solders:

1. The ASIC is marked DNP and excluded from the JLCPCB CPL, so the pick-and-place program never touches it.
2. Windowed exposed-pad paste (~50–70% grid coverage — never a 100% flood) + a tented/epoxy-filled via-in-pad stitch under the EP into the GND/thermal plane.
3. A hot-air keep-out ring protects the ESP32-S3 and LoRa modules during hand-reflow.
4. ENIG finish is the family default (flat, coplanar lands for fine-pitch dies).

The salvage moat is the cost advantage. D-Central has repaired 2,500+ miners; its captive stream of dead S17/T17 hashboards yields graded BM1397 dies at ~$0–2 each versus $12–50 for new chips — turning industrial e-waste into home space heaters. Chip-generation choice dominates chip count (4× BM1370 beats 6× BM1366 on TH/s, J/TH, and assembly), so the line leads with the cheapest, deepest-salvage chip and scales up.

⚠️ Every cost figure in this repo is a worked estimate and needs a live JLCPCB quote before the BOM and geometry are locked. The DFM strategy, panelization, feeder economics, and cost framework are summarized in UNIVERSAL_BOM_LOCK.md.

We hold ourselves to the same standard as DCENT_Toolbox: state plainly what is proven and what is not. DCENT_axe is a serious open-hardware design that has not yet been fabricated or mined on.

Roadmap:

• Phase 0 — DONE & committed: firmware LoRa/mesh crate, universal mechanical contract + BOM lock + geometry pack, ported KiCad/JLCPCB toolchain, BM1397 Single/Quad/Hex variants.
• Phase 1 — NEXT: build the universal common-platform schematic in KiCad, ERC → 0.
• Phases 2–4 — per SKU: place → layer-stack → RF-moat keepout → route (hand-route the SX1262 feedline) → copper pours → DRC-0 → JLCPCB gate → fabrication package.
• Phase 5: cross-verify + first-article bring-up runbooks.

dcent-axe/
├── README.md                              ← you are here
├── UNIVERSAL_MECHANICAL_CONTRACT.md       ← binding mech law (frozen vs. per-chip)
├── COMMON_PLATFORM_SCHEMATIC_SKELETON.md  ← shared electrical platform (blocks, nets, GPIO map)
├── UNIVERSAL_BOM_LOCK.md                  ← locked LCSC parts + certification analysis
├── PHASE0_READINESS.md                    ← toolchain go/no-go checklist
├── BOARD_VERSION_REGISTRY.md              ← the 9### ("over 9000") board-version namespace, claimed per SKU
├── _geometry/                             ← KiCad-read dims + corrected ASIC footprints + outlines
│   ├── GEOMETRY_PACK.md
│   └── footprints/                        ← BM1397 (corrected) + BM1366/68/70 + KF1950 (ref)
├── dcent-axe-BM1397/                      ← LEAD board (Single/Quad/Hex) — scaffolded + scripts/
├── dcent-axe-BM1368/                      ← next SKU to build out
├── dcent-axe-{BM1398,BM1366,BM1370,BM1362}/  ← scaffolded SKU placeholders (CLAUDE/docs/hardware)
└── dcent-axe-KF1950/                      ← MicroBT/WhatsMiner SKU (BitshokaNini ref vendored) — research target

The binding design rationale behind every decision — the mechanical, electrical, and BOM contracts, the geometry pack, and the certification analysis — lives in the contract documents in this repository: UNIVERSAL_MECHANICAL_CONTRACT.md, COMMON_PLATFORM_SCHEMATIC_SKELETON.md, UNIVERSAL_BOM_LOCK.md, and _geometry/GEOMETRY_PACK.md.

Board work uses the proven KiCad → JLCPCB toolchain (PowerShell + the kicad-superior MCP):

# Pre-fabrication gate: ERC / DRC / BOM / CPL
dcent-axe-BM1397/scripts/pre_jlcpcb_gate.ps1 -Strict

# Bulk autoroute (Freerouting 2.1.0)
dcent-axe-BM1397/scripts/run_freerouting.ps1 -MaxPasses 30

KiCad discipline (load-bearing): the schematic is the source of truth · snapshot the PCB before every MCP op · hand-route the RF feedline and controlled-impedance nets — never autoroute the SX1262 feedline.

Firmware tests and image-build notes live in the DCENT_OS for ESP devices project; this hardware project does not gate firmware builds.

All under one roof at github.com/DCentralTech — decentralize every layer: mining, tools, hardware, communication.

• DCENT_OS — open-source mining firmware for industrial Antminers (S9→S21) and ESP32 Bitaxe-class miners (Avalon + WhatsMiner scaffolded).
• DCENT_Toolbox — the open-source bench tool: scan, unlock, audit, flash, and prove — from your own machine.
• DCENT_axe — open-hardware Bitaxe-class boards (Solo / Quad / Hex) with integrated LoRa mesh.
• DCENT_Raven — LoRa-mesh accessory for any Bitaxe.

D-Central Technologies stewards the project's direction and decides which contributions merge upstream; contributors retain full fork rights under the open licenses. This preserves user freedom while keeping a clear, accountable design authority — the same model as DCENT_OS and DCENT_Toolbox.

Because this is safety-relevant mining hardware (high current, hot silicon, an intentional radio), contributions to the electrical, thermal, mechanical, or RF contracts are reviewed against the binding documents in this repo. Start with the Universal Mechanical Contract §5 conformance checklist before proposing a board change.

• Hardware designs: CERN-OHL-S-2.0 (strongly-reciprocal open hardware) — see LICENSE-HARDWARE.
• Firmware: GPL-3.0 (DCENT_OS for ESP devices).
• No hardcoded credentials, no cloud tether, no forced dev fee — community-facing, fully auditable.

Radio certification (read before building or selling a unit with the radio installed):

• FCC: the SX1262 module carries FCC ID 2ALPH-E22900M22S (Single Modular Approval, Part 15.247). This grant is inheritable only under conditions: max antenna gain ≤ 3 dBi, same type; the finished product must carry a Contains FCC ID: 2ALPH-E22900M22S label; the radio must not be co-located with another transmitter; 20 cm separation; and the assembled miner still needs Part 15 Subpart B unintentional-radiator compliance (the ASIC + buck switching noise is yours).
• Canada (ISED): NOT cleared. No IC certification number was found for this module — you cannot print "Contains IC:" on the product. A Canadian SKU needs a separate ISED certification (RSS-247) or an already-IC-certified module swap.
• EU: the 915 MHz part is the US/Canada-band variant; an EU SKU would use the 868 MHz E22 with its own CE-RED file and firmware TX duty-cycling.

No performance, efficiency, or certification claim in this repository is final until first-article bring-up plus a real accepted share. This is research/prototype open hardware — build, mine, and operate only hardware you own, in compliance with your local radio and electrical regulations.

D-Central Technologies is Canada's leading Bitcoin mining technology company — founded 2016 in Laval, Québec, self-described "Mining Hackers." With 2,500+ miners repaired and 400+ products, D-Central's core angle is turning institutional and industrial ASIC miners into Bitcoin space heaters for home use — and building the open-source tools, firmware, and now open hardware to do it.

DCENT_axe is that philosophy in silicon: home miners deserve hardware they can build, audit, repair, mesh, and own — fed by the e-waste the industry throws away.

Stack sats. Heat your home. Own your hardware. Send a raven.

If DCENT_axe is useful to you, please consider funding continued open-source development: d-central.tech/fund (Stripe + BTCPay).