New answers tagged verilog
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Accepted
What could be wrong with my vivado simulation? The clock isn't alternating
It appears your view is zoomed in too much. The timestamps on waveforms show 1ps distance between marks, while your clock should have transitions every 5ns, i.e. 5000 times slower. You should zoom out....
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1
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JK flip flop behavior on startup in Verilog
The issue with your gate-level model is that it only represents an unknown in simulation using a single representation: 1'bx, which is overly pessimistic. The ...
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JK flip flop behavior on startup in Verilog
Using a gate-level model for sequential logic like a flip-flop is the wrong tool for the job in Verilog. The right tool for the job is a behavioral model.
Your model with the ...
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2
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Accepted
Why is the waveform not matching? (2 clock delay in FSM code)
This code in the testbench is full of Verilog simulation race conditions:
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