Questions tagged [ddr4]
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28 questions
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What is the critical gap for splitting the reference plane - Length matching
Assume you want to route a LPDDR4 memory. You enter a situation were you cannot no longer proceed because there is a via blocking your path. So you decide to remove that via and route your trace.
But ...
- 1,464
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Serpentine routing between vias at under the BGA package - Length matching
I wonder if it's OK to use serpentine routing between vias at under the BGA package.
If you look at DDR0_DQ27, you can see that I using that area to perform length matching by use serpentine routing ...
- 1,464
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DDR4 bit, byte, nibble swapping
I’m working on a DDR4 PCB layout and want to confirm the allowed rules for bit swapping, byte lane swapping, and nibble swapping, especially when ECC or CRC is enabled.
From what I understand so far:
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How can one memory channel support two dimm slots without signal integrity problem？
Some motherboards have 4 DIMM slots. Every two DIMM slots are connected to one memory channel. I have no idea how this just works.
For control signals like clock and address, a daisy chain is needed. ...
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Please Review my PCB stackup
I am developing an AM6442 SOM.
This is PCB layer stackup
This my layer assignments:
L1: Signals - Low Speed (UART, QEP, PWM, DeltaSigma ADC, GPIO, JTAG)
L2: Ground Plane
L3: Signals - HighSpeed ...
- 529
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3
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Is my meander a bad idea?
Autodesk Eagle's Meander:
My compact meander:
How bad of an idea is it to use "My compact meander" meander instead of the Eagles's version? The Autodesk Eagle's meander tool is very bad, ...
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How to handle unused 32-bit data, dqs and dbi on DDR4 SODIMM module
In a design, I have used a DDR4 SODIMM module, which has 64-bit data, thus 8 groups of data (DQ), DQS and DBI.
However, I will only use the lower 32 bit on the module, thus have to handle the ...
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Difference between using a single x16 DDR4 memory device or two x8 DDR4 memory devices
I'm working on a design that has a 16 bit DDR4 memory controller and also has a reference schematic. The reference design has two separate x8 DDR4 memory devices connected to the controller DQ[0:7] ...
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1
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DDR4 Routing Consideration on pcb (no DIMM)
I need to route DDR4x2(3200MHz) to my FPGA.
my stackup is 12 Layers, TH Via only, and thickness of 2mm PCB.
my question regard which layer to route the FPGA to DDR4, when the two component on the TOP(...
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Modern DDR4 memory access latency system analysis
The memory access latency for the Intel Core i7-11800H (source: chipsandcheese, cpu latency for Intel Core i7-11800H), using DDR4-3200, reveals specific timings: 1 ns for L1, 3 ns for L2, and 13 ns ...
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Why is there a tRRD in DDR3? There does not seem to be a resource conflict between different banks
In DDR3, bank activation is specific to the Bank, for different banks, they all have their own sense amp and do not seem to affect each other, so why would there be tRRD?
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What's the purpose of the DDR4 1X, 2X and 4X refresh modes?
The DDR4 specification defines 1x, 2x and 4x refresh modes as follows:
The default Refresh rate mode is fixed 1x mode where Refresh commands
should be issued with the normal rate, i.e., tREFI1 = ...
- 431
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How do I length match different signal classes for DDR3 or DDR4 routing on a PCB?
DDR3 and DDR4 memory routing can be confusing to for length matching because of the many tolerances and specs of all the different busses.
How do I length match different signal classes for DDR3 or ...
- 93.2k
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What is mean by VREF Training in DDR4?
While going through DDR3 and DDR4, there is a term called vref. Where in DDR3 it is outside the DDR and for DDR4 it is inside the chip. Why we need training for it. What is the use of it.
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Memory density understanding
I am trying to understand DDR4 datasheet. All memory chips listed on page 3 have density equal to organization multiplication except 16Gb B-die and 32Gb A-die ones.
Let's pick K4A8G165WC. Chip have ...
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