Questions tagged [ddr]
Double Data Rate describes a computer bus that transfers data on both the rising and falling edges of the clock signal. Often used to describe SDRAM access.
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LPDDR4 T Branch topology layout routing length match
For LPDDR4 T Branch topology layout routing do I need to match the length of Level 1 branch also with A0 with other address group like A1 A2 etc should be also equally length match.
Level 1 branch ...
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Why does ECC add 1/4 more DRAM ICs with DDR5, rather than 1/8?
While shopping for 32 GiByte DDR5 ECC UDIMMs, I found pictures with 20 identical DRAM ICs, where I was expecting 18, because that's been the usual number for large DDR/DDR2/DDR3/DDR4 ECC UDIMMs, and I ...
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What is the critical gap for splitting the reference plane - Length matching
Assume you want to route a LPDDR4 memory. You enter a situation were you cannot no longer proceed because there is a via blocking your path. So you decide to remove that via and route your trace.
But ...
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How do I pass a clock signal through an FPGA while redriving it?
I would like to "pass through" a clock signal in an FPGA, while redriving it.
I would also like to calculate other signals synchronously with the clock and output them (to be sampled on ...
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How does Memory Controller in X86-64 CPU Address a 64-bit Integer using 64-bit Address?
Intro
I've watched the channel BranchEducation's video about Computer Memories, and read the first few sections of What Should Every Programmer Know About Memory to understand the memory internals.
I ...
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How are multiple DDR5 DIMMs wired into to the same channel?
This question is about how multiple DDR5 DIMMs in the same memory channel are wired to the processor. This is mostly an electrical engineering question, and the goal to answer this question:
Will re-...
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In LPDDR6, does Write store 2B System Meta Data into a bank's metadata registers? Is a MATA WRITE needed to store this data back into the array?
When Write or Read commands are issued to a LPDDR6 SRAM device, Meta-Write/Meta-Read
commands can be distinguished from normal Write/Read commands by PAMM segment hit or
miss in a target bank and ...
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DDR with ARTIX 7 is not initialaizing
We are using Artix7 200T in our design.
We are using two independent DDR3L (MT41K512M16VRP-107 AAT) interface in our card.
Both with 8Gb capacity with 16 bit data width.
Both DDR is completely ...
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Ferrite bead vs feed through capacitors for LPDDR4
I am designing a TI's AM6442 processor board
I am using SK-AM64x their development board as desgin reference.
There are two version an older and a newer
Old version schemtatic:
New version ...
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LPDDR4 layout, should we avoid having signals in same byte group on different layers?
Is it a bad idea to route intra byte DQx on different layers?
I am trying to interface AM6442 to LPDDR4 16bit. I have followed every constraint in TI's DDR layout guidelines to the letter, ...
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Is my meander a bad idea?
Autodesk Eagle's Meander:
My compact meander:
How bad of an idea is it to use "My compact meander" meander instead of the Eagles's version? The Autodesk Eagle's meander tool is very bad, ...
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Benefit of bank groups in DDR4 and beyond
I'm trying to understand how grouping the banks together can increase the throughput of DDRx. Reading into the sense amplifier appear to be the main bottleneck in DDRx throughput, however there is ...
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How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
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How can autorouting be done in Altium CircuitMaker?
I need to do autorouting in Altium CircuitMaker. I have only found information how to do autorouting in Altium Designer.
What I need to know is to set up rules and enviroment for autorouting with the ...
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DDR3 U-DIMM Signal Reference Plain
I am doing the PCB layout of a DDR3 U-DIMM and I have run into a perceived gap in the JEDEC DDR3 DIMM standards and am hoping to get some input from a DDR3 SME who could clarify the Address/Control ...
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