Bit-serial architecture
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In digital logic applications, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel word architectures, in which data values are sent all bits or a word at once along a group of wires.
All computers before 1951, and most of the early massive parallel processing machines used a bit-serial architecture—they were serial computers.
Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.[1]
Often N serial processors will take less FPGA area and have a higher total performance than a single N-bit parallel processor.
References[edit]
- ^ Peter B. Denyer and David Renshaw (1985). VLSI signal processing: a bit-serial approach. Addison-Wesley. ISBN 978-0-201-13306-6.
External links[edit]
- Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method
- BIT-Serial FIR filters with CSD Coefficients for FPGAs
