A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution

The rise of artificial intelligence (AI) is advancing at breakneck speed, pushing computing demands. At the same time, Moore’s Law slows, making monolithic devices increasingly cost-prohibitive and harder to scale. As traditional monolithic scaling hits the wall, the solution is to disaggregate the design into multiple dies, known as chiplets. These chiplets are mounted on a common substrate and presented in a single package. This modular approach forms the foundation of chiplet-based architectures that keep innovation moving forward.

Chiplet designs unlock new possibilities for performance, efficiency, and manufacturability. Arteris supports this transition with a purpose-built multi-die solution that accelerates integration and time-to-silicon for next-generation AI, automotive, and high-performance computing (HPC) systems.

Fig. 1: Chiplets enable a shift from scale-up to scale-out. (Source: Arteris)

Enabling scalable chiplet architectures

The expanded Arteris multi-die solution provides a foundational technology for rapid chiplet‑based innovation by delivering silicon‑proven network-on-chip (NoC) IP that ensures low‑latency, die‑to‑die communication. Automation tools are also included for chiplet system-on-chip (SoC) integration. This unified, standards-based approach enables the development of modular architectures that meet the demands of today’s leading-edge applications.

The multi-die solution supports homogeneous scaling by replicating identical chiplet designs across multiple dies to improve capacity and yield beyond reticle limits. In HPC and AI workloads, this approach makes it possible to duplicate a single processing tile, forming a larger, scalable compute fabric.

The solution also facilitates heterogeneous disaggregation, where individual dies are differentiated by function or process geometries. In automotive ADAS and LiDAR systems, this implementation places memory blocks on mature nodes for improved yield, while logic-intensive functions are implemented on advanced nodes.

Fig. 2: Multi-die use cases. (Source: Arteris)

Additionally, Arteris is fostering a standards-based chiplet ecosystem by collaborating across the semiconductor value chain, including major EDA providers, foundries, system integrators, and semiconductor intellectual property (SIP) suppliers. Integration with Cadence and Synopsys EDA tool flows and compatible leading foundry processes enables streamlined SoC creation and die-to-die connectivity. Through joint efforts with Arm, Andes, SiFive, and Tenstorrent, Arteris ensures interoperability across domain-specific SIPs, chiplets, and interconnect protocols. This end-to-end alignment accelerates time-to-market, reduces development cost and complexity, and empowers silicon innovators to meet the performance and scalability demands of AI, HPC, and automotive platforms.

Framework for seamless chiplet-based designs

The enhanced multi-die solution is designed for interoperability, supporting key industry standards, including UCIe, PCIe, and Arm AMBA specifications. This ensures compatibility with a broad ecosystem of die-to-die controllers, PHYs, IP blocks, and packaging tools. The core suite of purpose-built products includes Ncore cache coherent IP, FlexNoC interconnect IP, FlexGen smart NoC interconnect IP, Magillem Connectivity, and Magillem Registers. This forms the foundation for scalable, high-performance SoC and chiplet-based design.

• Ncore expands cache coherency across multiple chiplets to increase scalability and performance and to reduce the costs of multi-die systems. This allows seamless cache-coherent reads and writes across chiplets. The entire multi-chiplet assembly will appear as unified silicon to the application software. Each die contributes to a global memory map while benefiting from optimized local memory latency through a Non-Uniform Memory Access (NUMA) scheme. Ncore accommodates many topologies and is processor-agnostic, supporting integration across diverse system architectures. Designers can implement a partitioned design flow that synchronizes RTL, memory maps, and documentation across architectural, physical, and chiplet-level views, reducing manual effort and the likelihood of design errors.
• FlexNoC is physically aware and silicon-proven for high-performance, non-coherent communication across multi-die systems. It supports integration with commercially available die-to-die solutions, allowing designers to connect chiplets while maintaining scalability and modularity. FlexNoC is designed to deliver high-bandwidth data movement, supporting a broad range of configurations and topologies. Its adaptability makes it well-suited for chiplet-based architectures where efficient interconnect is critical to meeting performance and power goals.
• FlexGen, like FlexNoC, is built on a silicon-proven IP library and takes things to the next level by streamlining chiplet design by automating topology generation and optimization. This drastically reduces the time-consuming manual effort typically required to evaluate multiple topology configurations, performance objectives, and physical constraints, boosting design productivity while reducing wire length and latency. FlexGen accelerates chiplet design iteration, automating the process to minimize manual intervention. This workflow speeds up timing convergence and improves design consistency, even in large and complex chiplet-based systems.

To further help with chiplet-based designs, Arteris offers automation tools that accelerate the assembly and integration of disaggregated dies. Magillem Connectivity and Magillem Registers are engineered to work together within a unified framework, enabling consistent connectivity and memory map definition across chiplets. Built on a standards-based, IP-XACT-compliant foundation, these tools ensure interoperability across design teams and toolchains, supporting the architectural and physical partitioning required for complex multi-die chiplet systems.

• Magillem Connectivity is engineered to automate the assembly of chiplets and IP blocks, managing hierarchical relationships, inter-die connectivity, and configuration across physically disaggregated systems. Eliminating manual and error-prone integration tasks simplifies the creation of multi-die designs and improves reliability throughout the development flow. The tool facilitates early exploration of chiplet partitioning and provides a seamless transition from architectural definition to physical implementation, helping ensure design consistency and reducing costly late-stage changes. This automation accelerates development cycles and supports the scalability required for complex chiplet-based systems.
• Magillem Registers extends automation to the hardware/software interface in chiplet-based systems by maintaining a single source of truth for memory maps and register descriptions across multiple dies. This unified approach ensures consistency throughout the design, enabling accurate system-level validation across chiplet boundaries and simplifying downstream tasks such as traceability, compliance, and functional safety analysis. Designers can rapidly generate firmware header files and complete documentation directly from the centralized register specification. By supporting collaborative development across teams working on different dies, Magillem Registers helps reduce integration delays and errors in complex multi-die chiplet architectures.

Proven NoC IP and integration tools for the next wave of chiplets

The Arteris multi-die solution was created for the future of chip design, providing the tools and infrastructure needed to build modular, chiplet-based systems. By combining silicon-proven interconnect IP with support for coherent and non-coherent designs, and automation for SoC integration, Arteris helps developers shorten development cycles while optimizing power, performance, and area.

This platform supports various use cases, from automotive controllers and AI accelerators to data center systems. It enables design reuse, functional safety, and seamless scalability, allowing teams to meet demanding schedules and evolving application needs.

Arteris combines technical leadership with proven execution, helping design teams reduce risk and confidently bring advanced multi-die systems to market. Its unified toolset and automation framework provide a solid foundation for first-silicon success, strengthened by collaboration across the semiconductor value chain. Arteris delivers a path to innovation built on scalable, interoperable silicon design for companies facing the challenges of next-generation workloads. To learn more, visit arteris.com/multi-die.