Popular repositories Loading

1. cva6 cva6 Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   SystemVerilog

2. fucking-algorithm fucking-algorithm Public

   Forked from labuladong/fucking-algorithm

   刷算法全靠套路，认准 labuladong 就够了！English version supported! Crack LeetCode, not only how, but also why.

3. Clock-Domain-Crossing-Design Clock-Domain-Crossing-Design Public

   Forked from zhangzek/Clock-Domain-Crossing-Design

   Clock Domain Crossing Design（use MCP formulation without feedback）基于MCP不带反馈的跨时钟域设计

   Verilog

4. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

   SystemVerilog

5. bmm_core bmm_core Public

   riscv core for fan, keep learning

   SystemVerilog

6. hw hw Public

   Forked from nvdla/hw

   RTL, Cmodel, and testbench for NVDLA

   Verilog