This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
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Oct 19, 2023 - SystemVerilog
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verilog-tb
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This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of your .sv DUT module while offering logging of the results, and executing the list of commands in order.
verilog systemverilog hdl test-bench systemverilog-simulation verilog-tb verilog-testbenches systemverilog-test-bench
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Sep 5, 2021 - SystemVerilog
A collection of solutions to Project Euler problems implemented in Verilog. Each solution is written to be synthesizable and verified through simulation. This project is a fun and practical way to learn and explore digital design while solving challenging mathematical problems.
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Feb 8, 2025 - Verilog
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