A translator to translate RV32I to REBEL-6. Includes custom assemblers to output RV32I (and hopefully soon REBEL-6) MRCS-readable object files, and assembly level simulators to simulate RV32I and REBEL-6 assembly code execution
riscv balanced-ternary ternary risc-v instruction-set-simulator rv32i cpu-simulator ternary-computer binary-to-ternary rebel-6 rv32i-to-rebel binary-to-ternary-translation instruction-set-translation c-to-ternary-pipeline ternary-computing
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Updated
Jun 16, 2025 - C++