rust-osdev
diff --git a/‎uefi/src/proto/pci/mod.rs
Copy file name to clipboardExpand all lines: uefi/src/proto/pci/mod.rs
+42-1Lines changed: 42 additions & 1 deletion b/‎uefi/src/proto/pci/mod.rs
Copy file name to clipboardExpand all lines: uefi/src/proto/pci/mod.rs
+42-1Lines changed: 42 additions & 1 deletion
@@ -2,13 +2,15 @@
 
 //! PCI Bus specific protocols.
 
+use core::cmp::Ordering;
+
 use uefi_raw::protocol::pci::root_bridge::PciRootBridgeIoProtocolWidth;
 
 pub mod root_bridge;
 
 /// IO Address for PCI/register IO operations
 #[repr(C, packed)]
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
 pub struct PciIoAddress {
     /// Register number within the PCI device.
     pub reg: u8,
@@ -54,12 +56,30 @@ impl PciIoAddress {
     }
 }
 
+impl From<u64> for PciIoAddress {
+    fn from(value: u64) -> Self {
+        unsafe { core::mem::transmute(value) }
+    }
+}
+
 impl From<PciIoAddress> for u64 {
     fn from(value: PciIoAddress) -> Self {
         unsafe { core::mem::transmute(value) }
     }
 }
 
+impl PartialOrd for PciIoAddress {
+    fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
+        Some(self.cmp(other))
+    }
+}
+
+impl Ord for PciIoAddress {
+    fn cmp(&self, other: &Self) -> Ordering {
+        u64::from(*self).cmp(&u64::from(*other))
+    }
+}
+
 /// Trait implemented by all data types that can natively be read from a PCI device.
 /// Note: Not all of them have to actually be supported by the hardware at hand.
 pub trait PciIoUnit: Sized + Default {}
@@ -95,3 +115,24 @@ fn encode_io_mode_and_unit<U: PciIoUnit>(mode: PciIoMode) -> PciRootBridgeIoProt
         _ => unreachable!("Illegal PCI IO-Mode / Unit combination"),
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use super::PciIoAddress;
+    use core::mem;
+
+    #[test]
+    fn test_pci_ioaddr_raw_conversion() {
+        assert_eq!(mem::size_of::<u64>(), mem::size_of::<PciIoAddress>());
+        let srcaddr = PciIoAddress {
+            reg: 0x11,
+            fun: 0x33,
+            dev: 0x55,
+            bus: 0x77,
+            ext_reg: 0x99bbddff,
+        };
+        let rawaddr: u64 = srcaddr.into();
+        let dstaddr = PciIoAddress::from(rawaddr);
+        assert_eq!(srcaddr, dstaddr);
+    }
+}